[Commit-gnuradio] r6085 - in gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga: lib tb top

[jcorgan]

Author: jcorgan
Date: 2007-07-30 17:24:22 -0600 (Mon, 30 Jul 2007)
New Revision: 6085

Modified:
   
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
   
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
   gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/
   
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
   
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
   
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
Log:
Work in progress, receiver debugging.

Modified: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
    2007-07-30 03:46:03 UTC (rev 6084)
+++ 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
    2007-07-30 23:24:22 UTC (rev 6085)
@@ -39,7 +39,16 @@
 
    // Temporary
    assign rx_strobe_o = ena_i;
-   assign rx_i_o = rx_in_i_i;
-   assign rx_q_o = rx_in_q_i;
 
+   reg [31:0] count;
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       count <= 32'b0;
+     else
+       count <= count + 32'b1;
+
+   assign rx_i_o = count[15:0];
+   assign rx_q_o = 16'hAA55;
+
 endmodule // radar_rx

Modified: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
===================================================================
--- 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
   2007-07-30 03:46:03 UTC (rev 6084)
+++ 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.sav
   2007-07-30 23:24:22 UTC (rev 6085)
@@ -1,4 +1,4 @@
-*-24.712317 37100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
+*-24.808464 9235000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
 @28
 radar_tb.clk
 radar_tb.ena
@@ -24,10 +24,11 @@
 @28
 radar_tb.uut.controller.tx_ctrl_o
 radar_tb.uut.controller.rx_ctrl_o
address@hidden
address@hidden
 -
 @28
 radar_tb.fifo_strobe
address@hidden
+radar_tb.fifo_i[15:0]
 @22
-radar_tb.fifo_i[15:0]
 radar_tb.fifo_q[15:0]


Property changes on: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top
___________________________________________________________________
Name: svn:ignore
   - *.qws
*.eqn
*.done
*.htm
*.rpt
*.ini
*.fsf
*.jam
*.jbc
*.pin
*.pof
*.rbf
*.smsg
*.sof
*.ttf
*.summary
db
Makefile
Makefile.in

   + *.qmsg
*.qws
*.eqn
*.done
*.htm
*.rpt
*.ini
*.fsf
*.jam
*.jbc
*.pin
*.pof
*.rbf
*.smsg
*.sof
*.ttf
*.summary
db
Makefile
Makefile.in


Modified: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
   2007-07-30 03:46:03 UTC (rev 6084)
+++ 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
   2007-07-30 23:24:22 UTC (rev 6085)
@@ -29,29 +29,6 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 
2003"
 set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
-set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/strobe_gen.v
 
 # Pin & Location Assignments
 # ==========================
@@ -398,4 +375,27 @@
 
 # end ENTITY(usrp_radar_mono)
 # --------------------
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
\ No newline at end of file
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
+set_global_assignment -name VERILOG_FILE dacpll.v
+set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
+set_global_assignment -name VERILOG_FILE ../lib/radar.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file

Modified: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
   2007-07-30 03:46:03 UTC (rev 6084)
+++ 
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
   2007-07-30 23:24:22 UTC (rev 6085)
@@ -59,3 +59,6 @@
 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a 
signal of width 16. The formal width of the signal in the module is 32.  Extra 
bits will be left dangling without any fanout logic." {  } { { 
"../lib/radar_control.v" "sr_tlook" { Text 
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 73 0 0 } }  } 0 
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a 
signal of width %3!d!. The formal width of the signal in the module is %4!d!.  
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal 
of width 16. The formal width of the signal in the module is 32.  Extra bits 
will be left dangling without any fanout logic." {  } { { 
"../lib/radar_control.v" "sr_tsw" { Text 
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } }  } 0 
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a 
signal of width %3!d!. The formal width of the signal in the module is %4!d!.  
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: 
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal 
of width 16. The formal width of the signal in the module is 32.  Extra bits 
will be left dangling without any fanout logic." {  } { { 
"../lib/radar_control.v" "sr_ton" { Text 
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 67 0 0 } }  } 0 
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a 
signal of width %3!d!. The formal width of the signal in the module is %4!d!.  
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) 
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): 
truncated value with size 32 to match size of target (12)" {  } { { 
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text 
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } }  } 0 10230 
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to 
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) 
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): 
truncated value with size 32 to match size of target (12)" {  } { { 
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text 
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } }  } 0 10230 
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to 
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done 
serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at 
serial_io.v(48): object \"write_done\" assigned a value but never read" {  } { 
{ "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text 
"H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } }  } 0 10036 
"Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but 
never read" 1 0 "" 0}