[Commit-gnuradio] r6040 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-07-20 16:15:42 -0600 (Fri, 20 Jul 2007)
New Revision: 6040

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_tb.v
   gnuradio/branches/developers/matt/u2f/control_lib/longfifo.v
Log:
block-ram based fifo to complement SRL16-based shortfifo, plus testbench


Added: gnuradio/branches/developers/matt/u2f/control_lib/fifo_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_tb.v                 
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_tb.v 2007-07-20 
22:15:42 UTC (rev 6040)
@@ -0,0 +1,124 @@
+module fifo_tb();
+   
+   reg clk, rst;
+   wire short_full, short_empty, long_full, long_empty;
+   reg         read, write;
+   
+   wire [7:0] short_do, long_do;
+   reg [7:0]  di;
+   
+   shortfifo #(.WIDTH(8)) shortfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),
+      .read(read & ~short_empty),.write(write & 
~short_full),.full(short_full),.empty(short_empty));
+   
+   longfifo #(.WIDTH(8), .SIZE(4)) longfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),
+      .read(read & ~long_empty),.write(write & 
~long_full),.full(long_full),.empty(long_empty));
+   
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #50 clk = ~clk;
+   
+   initial di = 8'hAE;
+   initial read = 0;
+   initial write = 0;
+
+   always @(posedge clk)
+     if(write)
+       di <= di + 1;
+   
+   always @(posedge clk)
+     begin
+       if(short_full != long_full)
+         $display("Error: FULL mismatch");
+       if(short_empty != long_empty)
+         $display("Error: EMPTY mismatch");
+       if(read & (short_do != long_do))
+         $display("Error: DATA mismatch");
+     end
+   
+   initial $dumpfile("fifo_tb.vcd");
+   initial $dumpvars(0,fifo_tb);
+
+   initial
+     begin
+       @(negedge rst);
+       @(posedge clk);
+       repeat (10)
+         @(posedge clk);
+       write <= 1;
+       @(posedge clk);
+       write <= 0;
+       @(posedge clk);
+       read <= 1;
+       @(posedge clk);
+       read <= 0;
+       @(posedge clk);
+
+       repeat(10)
+         begin
+            write <= 1;
+            @(posedge clk);
+            write <= 0;
+            @(posedge clk);
+            read <= 1;
+            @(posedge clk);
+            read <= 0;
+            //@(posedge clk);
+         end // repeat (10)
+       
+       write <= 1;
+       repeat (4)
+         @(posedge clk);
+       write <= 0;
+       @(posedge clk);
+       read <= 1;
+       repeat (4)
+         @(posedge clk);
+       read <= 0;
+       @(posedge clk);
+
+
+       write <= 1;
+       repeat (4)
+         @(posedge clk);
+       write <= 0;
+       @(posedge clk);
+       repeat (4)
+         begin
+            read <= 1;
+            @(posedge clk);
+            read <= 0;
+            @(posedge clk);
+         end
+
+       write <= 1;
+       @(posedge clk);
+       @(posedge clk);
+       read <= 1;
+       repeat (5)
+         @(posedge clk);
+       write <= 0;
+         @(posedge clk);
+         @(posedge clk);
+       read <= 0;
+       @(posedge clk);
+
+       write <= 1;
+       repeat (16)
+         @(posedge clk);
+       write <= 0;
+       @(posedge clk);
+       
+       read <= 1;
+       repeat (16)
+         @(posedge clk);
+       read <= 0;
+       @(posedge clk);
+                
+       repeat (10)
+         @(posedge clk);
+       $finish;
+     end
+endmodule // longfifo_tb

Added: gnuradio/branches/developers/matt/u2f/control_lib/longfifo.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/longfifo.v                
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/longfifo.v        
2007-07-20 22:15:42 UTC (rev 6040)
@@ -0,0 +1,81 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+//  based on block ram instead of SRL16's
+//  only one clock domain
+
+// Port A is write port, Port B is read port
+
+module longfifo
+  #(parameter WIDTH=32, SIZE=9)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     output full,
+     output empty);
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0]     read_state;
+   
+   always @(posedge clk)
+     if(rst)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+         .ena(1),
+         .wea(write),
+         .addra(wr_addr),
+         .dia(datain),
+         .doa(),
+
+         .clkb(clk),
+         .enb((read_state==PRE_READ)|read),
+         .web(0),
+         .addrb(rd_addr),
+         .dib(0),
+         .dob(dataout));
+
+   // Read side state
+   localparam    EMPTY = 0;
+   localparam    PRE_READ = 1;
+   localparam    READING = 2;
+
+   always @(posedge clk)
+     if(rst)
+       begin
+         read_state <= EMPTY;
+         rd_addr <= 0;
+       end
+     else
+       case(read_state)
+        EMPTY :
+          if(write)
+            begin
+               rd_addr <= wr_addr;
+               read_state <= PRE_READ;
+            end
+        PRE_READ :
+          begin
+             read_state <= READING;
+             rd_addr <= rd_addr + 1;
+          end
+        
+        READING :
+          if(read)
+            begin
+               if(rd_addr == wr_addr)
+                 read_state <= EMPTY;
+               else
+                 rd_addr <= rd_addr + 1;
+            end
+       endcase // case(read_state)
+
+   assign empty = (read_state != READING);
+   //assign      empty = (rd_addr == wr_addr);
+   assign        full = ((rd_addr - 1) == wr_addr);
+      
+endmodule // longfifo