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[Commit-gnuradio] r6013 - in gnuradio/trunk: config gr-radar-mono gr-rad
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From: |
jcorgan |
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Subject: |
[Commit-gnuradio] r6013 - in gnuradio/trunk: config gr-radar-mono gr-radar-mono/doc gr-radar-mono/src/fpga/lib gr-radar-mono/src/fpga/tb gr-radar-mono/src/fpga/top gr-radar-mono/src/python |
|
Date: |
Wed, 18 Jul 2007 14:20:30 -0600 (MDT) |
Author: jcorgan
Date: 2007-07-18 14:20:30 -0600 (Wed, 18 Jul 2007)
New Revision: 6013
Added:
gnuradio/trunk/gr-radar-mono/doc/registers.ods
Modified:
gnuradio/trunk/config/Makefile.am
gnuradio/trunk/gr-radar-mono/README
gnuradio/trunk/gr-radar-mono/doc/Makefile.am
gnuradio/trunk/gr-radar-mono/src/fpga/lib/cordic_nco.v
gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar.v
gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_config.vh
gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_control.v
gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_rx.v
gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_tx.v
gnuradio/trunk/gr-radar-mono/src/fpga/tb/
gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.sav
gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.v
gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
gnuradio/trunk/gr-radar-mono/src/python/radar_mono.py
gnuradio/trunk/gr-radar-mono/src/python/usrp_radar_mono.py
Log:
Merged r5945:6012 from jcorgan/radar into trunk. Updates gr-radar-mono
component. Trunk passes distcheck.
Modified: gnuradio/trunk/config/Makefile.am
===================================================================
--- gnuradio/trunk/config/Makefile.am 2007-07-18 20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/config/Makefile.am 2007-07-18 20:20:30 UTC (rev 6013)
@@ -46,7 +46,6 @@
grc_gr_radar_mono.m4 \
grc_gr_radio_astronomy.m4 \
grc_gr_rdf.m4 \
- grc_gr_radar_mono.m4 \
grc_gr_sounder.m4 \
grc_gr_trellis.m4 \
grc_gr_usrp.m4 \
Modified: gnuradio/trunk/gr-radar-mono/README
===================================================================
--- gnuradio/trunk/gr-radar-mono/README 2007-07-18 20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/README 2007-07-18 20:20:30 UTC (rev 6013)
@@ -1,14 +1,64 @@
-This GNU Radio component implements (will implement) a monostatic
-radar transmitter and receiver. It uses (will use) a custom FPGA
-build to generate a linear FM chip waveform directly in the USRP.
-Echo returns are (will be) recorded to a file.
+This GNU Radio component implements a monostatic radar transmitter
+and receiver. It uses a custom FPGA build to generate a linear
+FM chirp waveform directly in the USRP. Echo returns are (will be)
+recorded to a file for offline analysis.
-Currently, only a CW signal is generated for testing the frequency
-response of the FPGA code, AD9862, and daughterboard mixer.
+The LFM chirp can be up to 32 MHz in width, whose center frequency
+is set by which transmit daughter board is installed. This gives
+a range resolution of approximately 5 meters.
+Only boards in slot A are supported.
+
+The script to run is place in $prefix/bin:
+
+Usage: usrp_radar_mono.py [options]
+
+Options:
+ -h, --help show this help message and exit
+ -f FREQ, --frequency=FREQ
+ set transmitter center frequency to FREQ in Hz,
+ default is 0.0
+ -w FREQ, --chirp-width=FREQ
+ set LFM chirp bandwidth in Hz, default is 32000000.0
+ -a AMPLITUDE, --amplitude=AMPLITUDE
+ set waveform amplitude in % full scale, default is
+ 100,
+ --ton=TON set pulse on period in seconds, default is 5e-06,
+ --tsw=TSW set transmitter switching period in seconds, default
+ is 4.0625e-07,
+ --tlook=TLOOK set receiver look time in seconds, default is 5e-06,
+ --prf=PRF set pulse repetition frequency in Hz, default is
+ 10000.0,
+ -v, --verbose enable verbose output, default is disabled
+ -D, --debug enable debugging output, default is disabled
+
+The transmitter creates a LFM chirp, evenly centered on the supplied frequency.
+The four timing parameters are:
+
+ton Chirp on time in seconds.
+
+tsw Transmitter switching time in seconds. This the delay after the chirp
+ is transmitted before the receiver is enabled. These two (tsw and ton)
+ parameters determine the minimum range of the radar.
+
+tlook The the amount of time in seconds the receiver is enabled to record
+ echo responses ("look" time). This parameter determines the maximum
+ radar range that can be measured, though transmitter power will also
+ limit return strength and practical range.
+
+prf Pulse repetition frequency in Hz. This establishes to overall pulse
+ repetition period, which results in idle time between when the receiver
+ is turned off and the next transmitted chirp begins.
+
+Currently, only the transmitter is written. Also, there is not yet any sanity
+checks on the supplied parameters to the script.
+
+The receiver, when completed, will record the radar returns, preserving phase,
+into a file with metadata about each chirp.
+
This is experimental code.
Johnathan Corgan
Corgan Enterprises LLC
address@hidden
-7/11/2007
+7/18/2007
Modified: gnuradio/trunk/gr-radar-mono/doc/Makefile.am
===================================================================
--- gnuradio/trunk/gr-radar-mono/doc/Makefile.am 2007-07-18 20:08:11 UTC
(rev 6012)
+++ gnuradio/trunk/gr-radar-mono/doc/Makefile.am 2007-07-18 20:20:30 UTC
(rev 6013)
@@ -21,3 +21,4 @@
include $(top_srcdir)/Makefile.common
+EXTRA_DIST = registers.ods
\ No newline at end of file
Copied: gnuradio/trunk/gr-radar-mono/doc/registers.ods (from rev 6012,
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/doc/registers.ods)
===================================================================
(Binary files differ)
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/cordic_nco.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/cordic_nco.v 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/cordic_nco.v 2007-07-18
20:20:30 UTC (rev 6013)
@@ -47,7 +47,7 @@
assign ampl = ena_i ? ampl_i : 16'b0;
cordic tx_cordic
- (.clock(clk_i),.reset(rst_in),.enable(strobe_i),
+ (.clock(clk_i),.reset(rst_i),.enable(strobe_i),
.xi(ampl),.yi(16'b0),.zi(phase[31:16]),
.xo(data_i_o),.yo(data_q_o),.zo());
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar.v 2007-07-18 20:08:11 UTC
(rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar.v 2007-07-18 20:20:30 UTC
(rev 6013)
@@ -22,7 +22,7 @@
`include "../lib/radar_config.vh"
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
- tx_strobe_i,tx_dac_i_o,tx_dac_q_o,
+ tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
@@ -33,7 +33,7 @@
input s_strobe_i; // Configuration bus write
// Transmit subsystem
- input tx_strobe_i; // Generate an transmitter output sample
+ output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
@@ -45,26 +45,30 @@
output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
+ // Application control
wire reset; // Master application reset
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
-
- wire [15:0] ampl;
- wire [31:0] freq; // temporary
-
+ wire tx_ctrl; // Transmitter on control
+ wire rx_ctrl; // Receiver on control
+
+ // Configuration
+ wire [15:0] ampl; // Pulse amplitude
+ wire [31:0] fstart; // Chirp start frequency
+ wire [31:0] fincr; // Chirp per strobe frequency increment
+
radar_control controller
- (.clk_i(clk_i),.rst_i(1'b0),.ena_i(1'b1),
- .s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
- .reset_o(reset),.tx_ena_o(tx_enable),.rx_ena_o(rx_enable),
- .ampl_o(ampl),.freq_o(freq));
+
(.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
+
.reset_o(reset),.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
+ .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr));
radar_tx transmitter
- ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_enable),
- .ampl_i(ampl),.freq_i(freq),
- .strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
+ ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
+ .ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr),
+ .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
radar_rx receiver
- ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_enable),
+ ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl & 1'b0), // Disable receiver
for now
.strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
.rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_config.vh
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_config.vh 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_config.vh 2007-07-18
20:20:30 UTC (rev 6013)
@@ -24,8 +24,12 @@
`define FR_RADAR_MODE `FR_USER_0
`define bmFR_RADAR_MODE_RESET 32'h0001
-`define bmFR_RADAR_MODE_TX 32'h0002
-`define bmFR_RADAR_MODE_RX 32'h0004
+`define FR_RADAR_TON `FR_USER_1
+`define FR_RADAR_TSW `FR_USER_2
+`define FR_RADAR_TLOOK `FR_USER_3
+`define FR_RADAR_TIDLE `FR_USER_4
`define FR_RADAR_AMPL `FR_USER_5
-`define FR_RADAR_FREQ1N `FR_USER_8
+`define FR_RADAR_FSTART `FR_USER_6
+`define FR_RADAR_FINCR `FR_USER_7
+
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_control.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_control.v 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_control.v 2007-07-18
20:20:30 UTC (rev 6013)
@@ -21,39 +21,122 @@
`include "../lib/radar_config.vh"
-module radar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i,
- reset_o,tx_ena_o,rx_ena_o,ampl_o,freq_o);
+module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
+ reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
+ ampl_o,fstart_o,fincr_o);
// System interface
input clk_i; // Master clock @ 64 MHz
- input rst_i; // Master reset
- input ena_i; // Module level enable
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
- // Configuration outputs
+ // Control and configuration outputs
output reset_o;
- output tx_ena_o;
- output rx_ena_o;
+ output tx_strobe_o;
+ output tx_ctrl_o;
+ output rx_ctrl_o;
+ output [15:0] ampl_o;
+ output [31:0] fstart_o;
+ output [31:0] fincr_o;
- output [15:0] ampl_o;
- output [31:0] freq_o;
-
// Internal configuration
wire lp_ena;
wire dr_ena;
wire md_ena;
- wire [1:0] chirps;
+ wire [1:0] chirps;
+ wire [15:0] t_on;
+ wire [15:0] t_sw;
+ wire [15:0] t_look;
+ wire [31:0] t_idle;
// Configuration from host
- setting_reg #(`FR_RADAR_MODE)
sr_mode(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-
.out({chirps,md_ena,dr_ena,lp_ena,rx_ena_o,tx_ena_o,reset_o}));
+ setting_reg #(`FR_RADAR_MODE)
sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+
.out({chirps,md_ena,dr_ena,lp_ena,reset_o}));
- setting_reg #(`FR_RADAR_AMPL)
sr_ampl(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(ampl_o));
+ setting_reg #(`FR_RADAR_TON)
sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(t_on));
+
+ setting_reg #(`FR_RADAR_TSW)
sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(t_sw));
+
+ setting_reg #(`FR_RADAR_TLOOK)
sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(t_look));
+
+ setting_reg #(`FR_RADAR_TIDLE)
sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(t_idle));
+
+ setting_reg #(`FR_RADAR_AMPL)
sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(ampl_o));
- setting_reg #(`FR_RADAR_FREQ1N)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(freq_o));
+ setting_reg #(`FR_RADAR_FSTART)
sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(fstart_o));
+
+ setting_reg #(`FR_RADAR_FINCR)
sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(fincr_o));
+
+ // Pulse state machine
+ `define ST_ON 4'b0001
+ `define ST_SW 4'b0010
+ `define ST_LOOK 4'b0100
+ `define ST_IDLE 4'b1000
+
+ reg [3:0] state;
+ reg [31:0] count;
+
+ always @(posedge clk_i)
+ if (reset_o)
+ begin
+ state <= `ST_ON;
+ count <= 32'b0;
+ end
+ else
+ case (state)
+ `ST_ON:
+ if (count == {16'b0,t_on})
+ begin
+ state <= `ST_SW;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ `ST_SW:
+ if (count == {16'b0,t_sw})
+ begin
+ state <= `ST_LOOK;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 24'b1;
+
+ `ST_LOOK:
+ if (count == {16'b0,t_look})
+ begin
+ state <= `ST_IDLE;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ `ST_IDLE:
+ if (count == t_idle)
+ begin
+ state <= `ST_ON;
+ count <= 24'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ default: // Invalid state, reset state machine
+ begin
+ state <= `ST_ON;
+ count <= 32'b0;
+ end
+ endcase
+ assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
+ assign tx_ctrl_o = (state == `ST_ON);
+ assign rx_ctrl_o = (state == `ST_LOOK);
+
endmodule // radar_control
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_rx.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_rx.v 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_rx.v 2007-07-18
20:20:30 UTC (rev 6013)
@@ -22,8 +22,8 @@
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-module
radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,rx_in_i_i,rx_in_q_i,
- rx_i_o,rx_q_o,rx_strobe_o);
+module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,
+ rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
@@ -36,7 +36,7 @@
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
-
+
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output rx_strobe_o;
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_tx.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_tx.v 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/lib/radar_tx.v 2007-07-18
20:20:30 UTC (rev 6013)
@@ -19,7 +19,10 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-module radar_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,tx_i_o,tx_q_o);
+module radar_tx(clk_i,rst_i,ena_i,strobe_i,
+ ampl_i,fstart_i,fincr_i,
+ tx_i_o,tx_q_o);
+
// System control
input clk_i;
input rst_i;
@@ -28,19 +31,29 @@
// Configuration
input [15:0] ampl_i;
- input [31:0] freq_i;
+ input [31:0] fstart_i;
+ input [31:0] fincr_i;
- // Output
+ // Chirp output
output [13:0] tx_i_o;
output [13:0] tx_q_o;
+ wire [15:0] cordic_i, cordic_q;
- wire [15:0] cordic_i, cordic_q;
+ // Chirp generator
+ reg [31:0] freq;
+ always @(posedge clk_i)
+ if (rst_i | ~ena_i)
+ freq <= fstart_i;
+ else
+ if (strobe_i)
+ freq <= freq + fincr_i;
+
cordic_nco
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
- .ampl_i(ampl_i),.freq_i(freq_i),.phs_i(0),
+ .ampl_i(ampl_i),.freq_i(freq),.phs_i(0),
.data_i_o(cordic_i),.data_q_o(cordic_q));
- assign tx_i_o = cordic_i[13:0];
- assign tx_q_o = cordic_q[13:0];
+ assign tx_i_o = cordic_i[13:0];
+ assign tx_q_o = cordic_q[13:0];
endmodule // radar_tx
Property changes on: gnuradio/trunk/gr-radar-mono/src/fpga/tb
___________________________________________________________________
Name: svn:ignore
- Makefile
Makefile.in
sar_tb
out
*.out*
*.vcd
+ Makefile
Makefile.in
radar_tb
out
*.out*
*.vcd
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.sav
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.sav 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.sav 2007-07-18
20:20:30 UTC (rev 6013)
@@ -1,17 +1,17 @@
-*-20.535921 1109000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
+*-24.712317 37100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
@28
radar_tb.clk
radar_tb.ena
radar_tb.rst
radar_tb.uut.reset
-radar_tb.uut.tx_enable
-radar_tb.uut.rx_enable
@200
-
address@hidden
-radar_tb.uut.freq[31:0]
address@hidden
address@hidden
radar_tb.uut.controller.ampl_o[15:0]
address@hidden
+radar_tb.uut.controller.fstart_o[31:0]
+radar_tb.uut.controller.fincr_o[31:0]
+radar_tb.uut.transmitter.freq[31:0]
@200
-
@28
@@ -21,3 +21,6 @@
radar_tb.uut.tx_dac_q_o[13:0]
@200
-
address@hidden
+radar_tb.uut.controller.tx_ctrl_o
+radar_tb.uut.controller.rx_ctrl_o
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.v 2007-07-18 20:08:11 UTC
(rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/tb/radar_tb.v 2007-07-18 20:20:30 UTC
(rev 6013)
@@ -36,7 +36,7 @@
reg s_strobe;
// DAC bus
- reg tx_strobe;
+ wire tx_strobe;
wire [13:0] tx_dac_i;
wire [13:0] tx_dac_q;
@@ -55,14 +55,10 @@
radar uut
(.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe),
- .tx_strobe_i(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
+ .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
.rx_strobe_i(rx_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
.rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q));
- // Drive tx_strobe @ half clock rate
- always @(posedge clk)
- tx_strobe <= ~tx_strobe;
-
// Start up initialization
initial
begin
@@ -72,7 +68,6 @@
saddr = 0;
sdata = 0;
s_strobe = 0;
- tx_strobe = 0;
rx_strobe = 1;
rx_adc_i = 0;
rx_adc_q = 0;
@@ -122,54 +117,85 @@
end
endtask // reset
- // Enable/disable transmitter
- task enable_tx;
- input enabled;
-
+ // Waveform on time
+ task set_ton;
+ input [23:0] t_on;
+
begin
- mode = enabled ? (mode | `bmFR_RADAR_MODE_TX) : (mode &
~`bmFR_RADAR_MODE_TX);
- write_cfg_register(`FR_RADAR_MODE, mode);
+ write_cfg_register(`FR_RADAR_TON, t_on);
end
- endtask // enable_tx
-
- // Enable/disable receiver
- task enable_rx;
- input enabled;
-
+ endtask // set_ton
+
+ // Transmitter switching time
+ task set_tsw;
+ input [23:0] t_sw;
+
begin
- mode = enabled ? (mode | `bmFR_RADAR_MODE_RX) : (mode &
~`bmFR_RADAR_MODE_RX);
- write_cfg_register(`FR_RADAR_MODE, mode);
+ write_cfg_register(`FR_RADAR_TSW, t_sw);
end
- endtask // enable_rx
-
- // Waveform amplitude
- task set_amplitude;
- input [13:0] amp;
+ endtask // t_sw
+ // Receiver look time
+ task set_tlook;
+ input [23:0] t_look;
+
begin
- write_cfg_register(`FR_RADAR_AMPL, amp);
+ write_cfg_register(`FR_RADAR_TLOOK, t_look);
end
- endtask // set_amplitude
+ endtask // set_tlook
- // Waveform frequency
- task set_frequency;
- input [31:0] freq;
+ // Inter-pulse idle time
+ task set_tidle;
+ input [23:0] t_idle;
begin
- write_cfg_register(`FR_RADAR_FREQ1N, freq);
+ write_cfg_register(`FR_RADAR_TIDLE, t_idle);
end
- endtask // frequency
+ endtask // set_tidle
+ // Chirp amplitude
+ task set_ampl;
+ input [31:0] ampl;
+
+ begin
+ write_cfg_register(`FR_RADAR_AMPL, ampl);
+ end
+ endtask // set_ampl
+
+ // Chirp start frequency
+ task set_fstart;
+ input [31:0] fstart;
+
+ begin
+ write_cfg_register(`FR_RADAR_FSTART, fstart);
+ end
+ endtask // set_fstart
+
+ // Chirp frequency increment
+ task set_fincr;
+ input [31:0] fincr;
+
+ begin
+ write_cfg_register(`FR_RADAR_FINCR, fincr);
+ end
+ endtask // set_fincr
+
// Test transmitter functionality
task test_tx;
begin
#20 set_reset(1);
- #20 set_amplitude(16'd9946);
- #20 set_frequency(32'h08000000);
- #20 enable_tx(1);
- #20 enable_rx(0);
+
+ #20 set_ton(320-1); // 5us on time
+ #20 set_tsw(26-1); // 406ns switching time
+ #20 set_tlook(320-1); // 5us look time
+ #20 set_tidle(3174-1); // 60us pulse period
+
+ #20 set_ampl(16'd9946);
+ #20 set_fstart(32'h80000000); // -16 to 16 MHz
+ #20 set_fincr (32'h0199999A);
+
#20 set_reset(0);
- #10000;
+ #200000;
end
endtask // test_tx
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-18 20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-18 20:20:30 UTC (rev 6013)
@@ -28,7 +28,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
@@ -397,4 +397,5 @@
# -------------------------
# end ENTITY(usrp_radar_mono)
-# --------------------
\ No newline at end of file
+# --------------------
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
\ No newline at end of file
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
===================================================================
(Binary files differ)
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-18 20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-18 20:20:30 UTC (rev 6013)
@@ -0,0 +1,140 @@
+{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design
file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified
as a design file for the current project, but contains definitions for 1 design
units and 1 entities in project" { } { } 0 0 "Using design file %1!s!, which
is not specified as a design file for the current project, but contains
definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
+{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using
design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not
specified as a design file for the current project, but contains definitions
for 10 design units and 10 entities in project" { } { } 0 0 "Using design
file %1!s!, which is not specified as a design file for the current project,
but contains definitions for %2!d! design units and %3!d! entities in project"
1 0 "" 0}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done
serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at
serial_io.v(48): object \"write_done\" assigned a value but never read" { } {
{ "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } } } 0 10036
"Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but
never read" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 "
"Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is
connected to a signal of width 7. The formal width of the signal in the module
is 8. Extra bits will be driven by GND." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be driven by GND." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a
signal of width 4. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is
connected to a signal of width 8. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "rate rx_strobe_gen 32
8 " "Warning: Port \"rate\" on the entity instantiation of \"rx_strobe_gen\" is
connected to a signal of width 32. The formal width of the signal in the module
is 8. Extra bits will be ignored." { } { { "../lib/radar_rx.v"
"rx_strobe_gen" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_rx.v" 62 0 0 } } } 0 0
"Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage11\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage10\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage9\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage8\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage7\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage6\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage5\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage4\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage3\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage2\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage1\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage0\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 59 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 56 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { } { } 0 0 "The following nets are
missing source, defaulting to GND" 1 0 "" 0}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { { "Warning"
"WSGN_TRI_BUS_MISSING_SOURCE_SUB"
"radar:radar_mono\|radar_control:controller\|rst_i " "Warning: Net
\"radar:radar_mono\|radar_control:controller\|rst_i\"" { } { {
"../lib/radar_control.v" "rst_i" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 -1 0 } } } 0
0 "Net \"%1!s!\"" 1 0 "" 0} } { } 0 0 "The following nets are missing source,
defaulting to GND" 0 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is
connected to a signal of width 11. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a
signal of width 20. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a
signal of width 4. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND "
"Warning: Reduced register
\"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck
data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin
\"MYSTERY_SIGNAL\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\"
stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[0\] GND " "Warning: Pin
\"tx_b\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[1\] GND " "Warning: Pin
\"tx_b\[1\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[2\] GND " "Warning: Pin
\"tx_b\[2\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[3\] GND " "Warning: Pin
\"tx_b\[3\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[4\] GND " "Warning: Pin
\"tx_b\[4\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[5\] GND " "Warning: Pin
\"tx_b\[5\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[6\] GND " "Warning: Pin
\"tx_b\[6\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[7\] GND " "Warning: Pin
\"tx_b\[7\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[8\] GND " "Warning: Pin
\"tx_b\[8\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[9\] GND " "Warning: Pin
\"tx_b\[9\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[10\] GND " "Warning: Pin
\"tx_b\[10\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[11\] GND " "Warning: Pin
\"tx_b\[11\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[12\] GND " "Warning: Pin
\"tx_b\[12\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[13\] GND " "Warning: Pin
\"tx_b\[13\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TXSYNC_B GND " "Warning: Pin
\"TXSYNC_B\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin
\"usbrdy\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[0\] " "Warning: No output dependent
on input pin \"rx_b_a\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[1\] " "Warning: No output dependent
on input pin \"rx_b_a\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[2\] " "Warning: No output dependent
on input pin \"rx_b_a\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[3\] " "Warning: No output dependent
on input pin \"rx_b_a\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[4\] " "Warning: No output dependent
on input pin \"rx_b_a\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[5\] " "Warning: No output dependent
on input pin \"rx_b_a\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[6\] " "Warning: No output dependent
on input pin \"rx_b_a\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[7\] " "Warning: No output dependent
on input pin \"rx_b_a\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[8\] " "Warning: No output dependent
on input pin \"rx_b_a\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[9\] " "Warning: No output dependent
on input pin \"rx_b_a\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[10\] " "Warning: No output dependent
on input pin \"rx_b_a\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[11\] " "Warning: No output dependent
on input pin \"rx_b_a\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[0\] " "Warning: No output dependent
on input pin \"rx_b_b\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[1\] " "Warning: No output dependent
on input pin \"rx_b_b\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[2\] " "Warning: No output dependent
on input pin \"rx_b_b\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[3\] " "Warning: No output dependent
on input pin \"rx_b_b\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[4\] " "Warning: No output dependent
on input pin \"rx_b_b\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[5\] " "Warning: No output dependent
on input pin \"rx_b_b\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[6\] " "Warning: No output dependent
on input pin \"rx_b_b\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[7\] " "Warning: No output dependent
on input pin \"rx_b_b\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[8\] " "Warning: No output dependent
on input pin \"rx_b_b\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[9\] " "Warning: No output dependent
on input pin \"rx_b_b\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[10\] " "Warning: No output dependent
on input pin \"rx_b_b\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[11\] " "Warning: No output dependent
on input pin \"rx_b_b\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info:
Pin MYSTERY_SIGNAL has GND driving its datain port" { } { {
"usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" }
} } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL
} "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" ""
{ Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3
has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } {
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1
0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[0\] GND " "Info: Pin
tx_b\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[0\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[1\] GND " "Info: Pin
tx_b\[1\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[1\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[1] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[2\] GND " "Info: Pin
tx_b\[2\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[2\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[2] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[3\] GND " "Info: Pin
tx_b\[3\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[3\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[3] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[4\] GND " "Info: Pin
tx_b\[4\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[4\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[4] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[5\] GND " "Info: Pin
tx_b\[5\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[5\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[5] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[6\] GND " "Info: Pin
tx_b\[6\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[6\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[6] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[7\] GND " "Info: Pin
tx_b\[7\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[7\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[7] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[8\] GND " "Info: Pin
tx_b\[8\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[8\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[8] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[9\] GND " "Info: Pin
tx_b\[9\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[9\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[9] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[10\] GND " "Info: Pin
tx_b\[10\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[10\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[10] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[11\] GND " "Info: Pin
tx_b\[11\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[11\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[11] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[12\] GND " "Info: Pin
tx_b\[12\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[12\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[12] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[13\] GND " "Info: Pin
tx_b\[13\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[13\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[13] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXSYNC_B GND " "Info: Pin
TXSYNC_B has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXSYNC_B" } } } }
{ "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXSYNC_B }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
TXSYNC_B } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin
usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } }
} } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tlook" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 63 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tsw" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 60 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ton" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 57 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 6. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 54 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tlook" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 64 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tsw" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 61 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ton" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 58 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 6. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
Modified: gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.v 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/fpga/top/usrp_radar_mono.v 2007-07-18
20:20:30 UTC (rev 6013)
@@ -142,7 +142,7 @@
// Top level application
radar radar_mono (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
- .tx_strobe_i(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+ .tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
.rx_strobe_i(rx_sample_strobe),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
.rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
);
@@ -172,7 +172,7 @@
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(),.decim_rate(),
- .tx_sample_strobe(tx_sample_strobe),.strobe_interp(),
+ .tx_sample_strobe(),.strobe_interp(), // tx_sample_strobe now generated
by radar transmitter module
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
.tx_empty(tx_empty),
.debug_0(),.debug_1(),
Modified: gnuradio/trunk/gr-radar-mono/src/python/radar_mono.py
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/python/radar_mono.py 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/python/radar_mono.py 2007-07-18
20:20:30 UTC (rev 6013)
@@ -30,38 +30,33 @@
#-----------------------------------------------------------------------
FR_RADAR_MODE = usrp.FR_USER_0 # Operational mode
bmFR_RADAR_MODE_RESET = 1 << 0 # bit 0: active high reset
-bmFR_RADAR_MODE_TX = 1 << 1 # bit 1: enable transmitter
-#bmFR_RADAR_MODE_RX = 1 << 2 # bit 2: enable receiver
-#bmFR_RADAR_MODE_LP = 1 << 3 # bit 3: enable digital loopback
-#bmFR_RADAR_MODE_DR = 1 << 4 # bit 4: enable on-board deramping
-#bmFR_RADAR_MODE_MD = 1 << 5 # bit 5: enable echo metadata
-#bmFR_RADAR_MODE_CHIRPS = 3 << 6 # bit 6,7: number of chirp center
frequencies
+#bmFR_RADAR_MODE_LP = 1 << 1 # bit 1: enable digital loopback
+#bmFR_RADAR_MODE_DR = 1 << 2 # bit 2: enable on-board deramping
+#bmFR_RADAR_MODE_MD = 1 << 3 # bit 3: enable echo metadata
+#bmFR_RADAR_MODE_CHIRPS = 3 << 4 # bit 4,5: number of chirp center
frequencies
-#FR_RADAR_TON = usrp.FR_USER_1 # 16-bit transmitter on time in clocks
-#FR_RADAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in
clocks
-#FR_RADAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks
-#FR_RADAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time
+FR_RADAR_TON = usrp.FR_USER_1 # 16-bit transmitter on time in clocks
+FR_RADAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in
clocks
+FR_RADAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks
+FR_RADAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time
FR_RADAR_AMPL = usrp.FR_USER_5 # 16-bit pulse amplitude (2s
complement) into CORDIC
-#FR_RADAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency
-#FR_RADAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit
clock
+FR_RADAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency
+FR_RADAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit
clock
# These are for phase II development
+#FR_RADAR_FREQ1N = usrp.FR_USER_8 # 24-bit N register for chirp #1
+#FR_RADAR_FREQ1R = usrp.FR_USER_9 # 24-bit R register for chirp #1
+#FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit control register for chirp #1
+#FR_RADAR_FREQ2N = usrp.FR_USER_11 # 24-bit N register for chirp #2
+#FR_RADAR_FREQ2R = usrp.FR_USER_12 # 24-bit R register for chirp #2
+#FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit control register for chirp #2
+#FR_RADAR_FREQ3N = usrp.FR_USER_14 # 24-bit N register for chirp #3
+#FR_RADAR_FREQ3R = usrp.FR_USER_15 # 24-bit R register for chirp #3
+#FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit control register for chirp #3
+#FR_RADAR_FREQ4N = usrp.FR_USER_17 # 24-bit N register for chirp #4
+#FR_RADAR_FREQ4R = usrp.FR_USER_18 # 24-bit R register for chirp #4
+#FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit control register for chirp #4
-# Temporarily use this for transmitter frequency calibration
-FR_RADAR_FREQ1N = usrp.FR_USER_8 # 24-bit N register for chirp #1
-
-FR_RADAR_FREQ1R = usrp.FR_USER_9 # 24-bit R register for chirp #1
-FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit control register for chirp #1
-FR_RADAR_FREQ2N = usrp.FR_USER_11 # 24-bit N register for chirp #2
-FR_RADAR_FREQ2R = usrp.FR_USER_12 # 24-bit R register for chirp #2
-FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit control register for chirp #2
-FR_RADAR_FREQ3N = usrp.FR_USER_14 # 24-bit N register for chirp #3
-FR_RADAR_FREQ3R = usrp.FR_USER_15 # 24-bit R register for chirp #3
-FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit control register for chirp #3
-FR_RADAR_FREQ4N = usrp.FR_USER_17 # 24-bit N register for chirp #4
-FR_RADAR_FREQ4R = usrp.FR_USER_18 # 24-bit R register for chirp #4
-FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit control register for chirp #4
-
#-----------------------------------------------------------------------
# Transmitter object. Uses usrp_sink, but only for a handle to the
# FPGA registers.
@@ -74,27 +69,61 @@
self._u = usrp.sink_s(fpga_filename='usrp_radar_mono.rbf')
self._subdev_spec = (0,0); # FPGA code only implements side A
self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
+ self._ton_ticks = 0
+ self._tsw_ticks = 0
+ self._tlook_ticks = 0
+ self._tidle_ticks = 0
+
if self._verbose:
print "Using", self._subdev.name(), "for radar transmitter."
- def tune(self, center_freq, waveform_freq):
+ def set_ton(self, ton):
+ self._ton_ticks = 2*(int(ton*64e6)/2)-1 # Even number, then subtract 1
+ if self._verbose:
+ print "Setting pulse on time to", ton, " sec
("+`self._ton_ticks+1`+" ticks)"
+ self._u._write_fpga_reg(FR_RADAR_TON, self._ton_ticks)
+
+ def set_tsw(self, tsw):
+ self._tsw_ticks = 2*(int(tsw*64e6)/2)-1 # Even number, then subtract 1
+ if self._verbose:
+ print "Setting pulse switching time to", tsw, " sec
("+`self._tsw_ticks+1`+" ticks)"
+ self._u._write_fpga_reg(FR_RADAR_TSW, self._tsw_ticks)
+
+ def set_tlook(self, tlook):
+ self._tlook_ticks = 2*(int(tlook*64e6)/2)-1 # Even number, then
subtract 1
+ if self._verbose:
+ print "Setting receiver look time to", tlook, " sec
("+`self._tlook_ticks+1`+" ticks)"
+ self._u._write_fpga_reg(FR_RADAR_TLOOK, self._tlook_ticks)
+
+ def set_prf(self, prf):
+ period = 2*int(32e6/prf)
+ self._tidle_ticks =
period-(self._ton_ticks+self._tsw_ticks+self._tlook_ticks+3)-1
+ if self._verbose:
+ print "Setting PRF to", prf, "Hz ("+`self._tidle_ticks+1`+" ticks
idle time)"
+ self._u._write_fpga_reg(FR_RADAR_TIDLE, self._tidle_ticks)
+
+ def set_amplitude(self, ampl):
+ self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction
+ if self._debug:
+ print "Writing amplitude register with:", hex(self._amplitude)
+ self._u._write_fpga_reg(FR_RADAR_AMPL, self._amplitude)
+
+ def set_freq(self, center_freq, chirp_width):
self._center_freq = center_freq
- self._waveform_freq = waveform_freq
- self._ftw = int(waveform_freq*(2**32)/32e6)
+ self._chirp_width = chirp_width
+ self._fstart = -int((chirp_width/2)*(2**32)/32e6)
+ self._fincr = int((chirp_width/16e6)*(2**32)/(self._ton_ticks+1))
+
if self._verbose:
print "Setting transmitter center frequency to", n2s(center_freq)
- print "Setting waveform frequency offset to", n2s(waveform_freq),
"with ftw of", self._ftw
+ print "Setting chirp width to", n2s(chirp_width), "Hz
"+"("+hex(self._fstart)+", "+hex(self._fincr)+")"
+
result = self._u.tune(0, self._subdev, center_freq)
if result == False:
raise RuntimeError("Failed to set transmitter frequency.")
- self._u._write_fpga_reg(FR_RADAR_FREQ1N, self._ftw)
+ self._u._write_fpga_reg(FR_RADAR_FSTART, self._fstart)
+ self._u._write_fpga_reg(FR_RADAR_FINCR, self._fincr)
- def set_amplitude(self, ampl):
- self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction
- if self._debug:
- print "Writing amplitude register with:", hex(self._amplitude)
- self._u._write_fpga_reg(FR_RADAR_AMPL, self._amplitude)
-
def start(self):
self._u.start()
@@ -181,48 +210,26 @@
self._debug = debug
self._mode = 0
- self._transmitting = False
self._trans = radar_tx(verbose=self._verbose, debug=self._debug)
self.set_reset(True)
- def set_amplitude(self, ampl):
- self._trans.set_amplitude(ampl)
-
- def tune(self, center_freq, waveform_freq):
- self._trans.tune(center_freq, waveform_freq)
-
def _write_mode(self):
if self._debug:
print "Writing mode register with:", hex(self._mode)
self._trans._u._write_fpga_reg(FR_RADAR_MODE, self._mode)
- def enable_tx(self, value):
+ def set_reset(self, value):
if value:
- if self._verbose:
- print "Enabling transmitter."
- self._mode |= bmFR_RADAR_MODE_TX
- self._transmitting = True
+ if self._debug:
+ print "Asserting reset."
+ self._mode |= bmFR_RADAR_MODE_RESET
else:
- if self._verbose:
- print "Disabling transmitter."
- self._mode &= ~bmFR_RADAR_MODE_TX
- self._transmitting = False
+ if self._debug:
+ print "De-asserting reset."
+ self._mode &= ~bmFR_RADAR_MODE_RESET
self._write_mode()
-
+
"""
- def enable_rx(self, value):
- if value:
- self._mode |= bmFR_RADAR_MODE_RX
- self._write_mode()
- self._rcvr.start()
- self._receiving = True
- else:
- self._rcvr.stop()
- self._mode &= ~bmFR_RADAR_MODE_RX
- self._write_mode()
- self._receiving = False
- """
- """
def set_loopback(self, value):
if value:
if self._verbose:
@@ -235,27 +242,32 @@
self._write_mode()
"""
- def set_reset(self, value):
- if value:
- if self._debug:
- print "Asserting reset."
- self._mode |= bmFR_RADAR_MODE_RESET
- else:
- if self._debug:
- print "De-asserting reset."
- self._mode &= ~bmFR_RADAR_MODE_RESET
- self._write_mode()
+ def set_ton(self, ton):
+ self._trans.set_ton(ton)
+
+ def set_tsw(self, tsw):
+ self._trans.set_tsw(tsw)
+
+ def set_tlook(self, tlook):
+ self._trans.set_tlook(tlook)
+
+ def set_prf(self, prf):
+ self._trans.set_prf(prf)
+ def set_amplitude(self, ampl):
+ self._trans.set_amplitude(ampl)
+
+ def set_freq(self, center_freq, chirp_width):
+ self._trans.set_freq(center_freq, chirp_width)
+ # set receiver center frequency
+
def start(self):
self._trans.start()
- self.enable_tx(True)
self.set_reset(False)
def stop(self):
self.set_reset(True)
self._trans.stop()
- if self._transmitting:
- self.enable_tx(False)
def __del__(self):
self.stop()
Modified: gnuradio/trunk/gr-radar-mono/src/python/usrp_radar_mono.py
===================================================================
--- gnuradio/trunk/gr-radar-mono/src/python/usrp_radar_mono.py 2007-07-18
20:08:11 UTC (rev 6012)
+++ gnuradio/trunk/gr-radar-mono/src/python/usrp_radar_mono.py 2007-07-18
20:20:30 UTC (rev 6013)
@@ -33,11 +33,18 @@
parser = OptionParser(option_class=eng_option)
parser.add_option("-f", "--frequency", type="eng_float", default=0.0,
help="set transmitter center frequency to FREQ in Hz,
default is %default", metavar="FREQ")
- # Temporary for debugging transmitter frequency response
- parser.add_option("-w", "--waveform-frequency", type="eng_float",
default=1e3,
- help="set waveform offset frequency to FREQ in Hz,
default is %default", metavar="FREQ")
+ parser.add_option("-w", "--chirp-width", type="eng_float", default=32e6,
+ help="set LFM chirp bandwidth in Hz, default is
%default", metavar="FREQ")
parser.add_option("-a", "--amplitude", type="eng_float", default=100,
help="set waveform amplitude in % full scale, default is
%default,")
+ parser.add_option("", "--ton", type="eng_float", default=5e-6,
+ help="set pulse on period in seconds, default is
%default,")
+ parser.add_option("", "--tsw", type="eng_float", default=406.25e-9,
+ help="set transmitter switching period in seconds,
default is %default,")
+ parser.add_option("", "--tlook", type="eng_float", default=5e-6,
+ help="set receiver look time in seconds, default is
%default,")
+ parser.add_option("", "--prf", type="eng_float", default=10e3,
+ help="set pulse repetition frequency in Hz, default is
%default,")
parser.add_option("-v", "--verbose", action="store_true", default=False,
help="enable verbose output, default is disabled")
parser.add_option("-D", "--debug", action="store_true", default=False,
@@ -69,8 +76,13 @@
msgq = gr.msg_queue()
s = radar(msgq=msgq,verbose=options.verbose,debug=options.debug)
+ s.set_ton(options.ton)
+ s.set_tsw(options.tsw)
+ s.set_tlook(options.tlook)
+ s.set_prf(options.prf)
s.set_amplitude(options.amplitude)
- s.tune(options.frequency, options.waveform_frequency)
+ s.set_freq(options.frequency, options.chirp_width)
+
s.start()
"""
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- [Commit-gnuradio] r6013 - in gnuradio/trunk: config gr-radar-mono gr-radar-mono/doc gr-radar-mono/src/fpga/lib gr-radar-mono/src/fpga/tb gr-radar-mono/src/fpga/top gr-radar-mono/src/python,
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