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[Commit-gnuradio] r5938 - in gnuradio/branches/developers/matt/u2f: cont
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5938 - in gnuradio/branches/developers/matt/u2f: control_lib firmware |
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Date: |
Wed, 11 Jul 2007 14:19:26 -0600 (MDT) |
Author: matt
Date: 2007-07-11 14:19:26 -0600 (Wed, 11 Jul 2007)
New Revision: 5938
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
gnuradio/branches/developers/matt/u2f/control_lib/mux4.v
gnuradio/branches/developers/matt/u2f/control_lib/mux8.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
gnuradio/branches/developers/matt/u2f/firmware/test1_main.c
Log:
fifo_int now stores its own command, no more setting reg
Property changes on: gnuradio/branches/developers/matt/u2f/control_lib
___________________________________________________________________
Name: svn:ignore
- a.out
*.vcd
+ a.out
*.vcd
*.lxt
*.sav
*.log
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-07-11 20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-07-11 20:19:26 UTC (rev 5938)
@@ -51,19 +51,14 @@
genvar i;
- wire [8:0] fl[0:7];
- wire [8:0] ll[0:7];
- wire [3:0] step[0:7];
- wire [7:0] read_go;
- wire [7:0] write_go;
- wire [1:0] read_port[0:7];
- wire [1:0] write_port[0:7];
- wire [2:0] dummy[0:7];
- wire clear [0:7];
+ wire go;
+
+ reg [2:0] port[0:7];
+ reg [3:0] read_src[0:3];
+ reg [3:0] write_src[0:3];
wire [7:0] done;
wire [7:0] error;
- wire [7:0] changed;
wire [31:0] buf_doa[0:7];
@@ -89,21 +84,50 @@
assign status = {error[7:0],done[7:0]};
- // Setting reg is {dummy[2:0], clear, read_port[1:0], write_port[1:0],
write_go, read_go, step[3:0], ll[8:0], fl[8:0]};
+ wire [31:0] fifo_ctrl;
+ setting_reg #(.my_addr(64))
+
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(fifo_ctrl),.changed(go));
+
+ integer k;
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<8;k=k+1)
+ port[k] <= 4; // disabled
+ else
+ for(k=0;k<8;k=k+1)
+ if(go & (fifo_ctrl[31:28]==k))
+ port[k] <= fifo_ctrl[27:25];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ read_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
+ read_src[k] <= fifo_ctrl[31:28];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ write_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
+ write_src[k] <= fifo_ctrl[31:28];
+
generate
for(i=0;i<8;i=i+1)
begin : gen_buffer
- setting_reg #(.my_addr(64+i))
-
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
-
.out({dummy[i],clear[i],read_port[i],write_port[i],write_go[i],read_go[i],step[i],ll[i],fl[i]}),.changed(changed[i]));
ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
(.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
.addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
- fifo_int fifo_int
-
(.clk(stream_clk),.rst(stream_rst),.firstline(fl[i]),.lastline(ll[i]),
-
.step(step[i]),.read_go(changed[i]&read_go[i]),.write_go(changed[i]&write_go[i]),
- .clear(changed[i]&clear[i]),.done(done[i]),.error(error[i]),
+ fifo_int #(.BUFF_NUM(i)) fifo_int
+ (.clk(stream_clk),.rst(stream_rst),
+ .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
+ .done(done[i]),.error(error[i]),
.en_o(buf_enb[i]),
.we_o(buf_web[i]),
.addr_o(buf_addrb[i]),
@@ -122,26 +146,28 @@
.rd_ready_o(rd_ready_o[i]),
.rd_empty_o(rd_empty_o[i])
);
+
+ // FIXME -- if it is a problem, maybe we don't need enables on these
muxes
mux4 #(.WIDTH(32))
- mux4_dat_i (.sel(write_port[i]),.i0(wr0_dat_i),.i1(wr1_dat_i),
+ mux4_dat_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_dat_i),.i1(wr1_dat_i),
.i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i]));
mux4 #(.WIDTH(1))
- mux4_write_i
(.sel(write_port[i]),.i0(wr0_write_i),.i1(wr1_write_i),
+ mux4_write_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_write_i),.i1(wr1_write_i),
.i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i]));
mux4 #(.WIDTH(1))
- mux4_wrdone_i (.sel(write_port[i]),.i0(wr0_done_i),.i1(wr1_done_i),
+ mux4_wrdone_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_done_i),.i1(wr1_done_i),
.i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i]));
mux4 #(.WIDTH(1))
- mux4_wrerror_i
(.sel(write_port[i]),.i0(wr0_error_i),.i1(wr1_error_i),
+ mux4_wrerror_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i),
.i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i]));
mux4 #(.WIDTH(1))
- mux4_read_i (.sel(read_port[i]),.i0(rd0_read_i),.i1(rd1_read_i),
+ mux4_read_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i),
.i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
mux4 #(.WIDTH(1))
- mux4_rddone_i (.sel(read_port[i]),.i0(rd0_done_i),.i1(rd1_done_i),
+ mux4_rddone_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_done_i),.i1(rd1_done_i),
.i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i]));
mux4 #(.WIDTH(1))
- mux4_rderror_i
(.sel(read_port[i]),.i0(rd0_error_i),.i1(rd1_error_i),
+ mux4_rderror_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_error_i),.i1(rd1_error_i),
.i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i]));
end // block: gen_buffer
endgenerate
@@ -158,131 +184,104 @@
assign wb_err_o = 1'b0; // Unused for now
assign wb_rty_o = 1'b0; // Unused for now
-
- // FIFO interface outputs
- integer j,k;
-
- // Read FIFO Outputs
- reg [2:0] wr_src[0:3];
- always @(posedge stream_clk)
- if(stream_rst)
- for(k=0;k<4;k=k+1)
- wr_src[k] <= 7;
- else
- for(k=0;k<4;k=k+1)
- for(j=0;j<8;j=j+1)
- if(changed[j] & write_go[j] & (write_port[j]==k))
- wr_src[k] <= j;
mux8 #(.WIDTH(1))
- mux8_wr_ready0(.sel(wr_src[0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+ mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]),
.i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
.i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
.i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),.o(wr0_ready_o));
mux8 #(.WIDTH(1))
- mux8_wr_full0(.sel(wr_src[0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+ mux8_wr_full0(.en(~write_src[0][3]),.sel(write_src[0][2:0]),
.i0(wr_full_o[0]), .i1(wr_full_o[1]),
.i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
.i5(wr_full_o[5]), .i6(wr_full_o[6]),
.i7(wr_full_o[7]),.o(wr0_full_o));
mux8 #(.WIDTH(1))
- mux8_wr_ready1(.sel(wr_src[1]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+ mux8_wr_ready1(.en(~write_src[1][3]),.sel(write_src[1][2:0]),
.i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
.i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
.i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),.o(wr1_ready_o));
mux8 #(.WIDTH(1))
- mux8_wr_full1(.sel(wr_src[1]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+ mux8_wr_full1(.en(~write_src[1][3]),.sel(write_src[1][2:0]),
.i0(wr_full_o[0]), .i1(wr_full_o[1]),
.i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
.i5(wr_full_o[5]), .i6(wr_full_o[6]),
.i7(wr_full_o[7]),.o(wr1_full_o));
mux8 #(.WIDTH(1))
- mux8_wr_ready2(.sel(wr_src[2]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+ mux8_wr_ready2(.en(~write_src[2][3]),.sel(write_src[2][2:0]),
.i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
.i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
.i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),.o(wr2_ready_o));
mux8 #(.WIDTH(1))
- mux8_wr_full2(.sel(wr_src[2]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+ mux8_wr_full2(.en(~write_src[2][3]),.sel(write_src[2][2:0]),
.i0(wr_full_o[0]), .i1(wr_full_o[1]),
.i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
.i5(wr_full_o[5]), .i6(wr_full_o[6]),
.i7(wr_full_o[7]),.o(wr2_full_o));
mux8 #(.WIDTH(1))
- mux8_wr_ready3(.sel(wr_src[3]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+ mux8_wr_ready3(.en(~write_src[3][3]),.sel(write_src[3][2:0]),
.i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
.i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
.i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),.o(wr3_ready_o));
-
+
mux8 #(.WIDTH(1))
- mux8_wr_full3(.sel(wr_src[3]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+ mux8_wr_full3(.en(~write_src[3][3]),.sel(write_src[3][2:0]),
.i0(wr_full_o[0]), .i1(wr_full_o[1]),
.i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
.i5(wr_full_o[5]), .i6(wr_full_o[6]),
.i7(wr_full_o[7]),.o(wr3_full_o));
- // Read FIFO Outputs
- reg [2:0] rd_src[0:3];
- always @(posedge stream_clk)
- if(stream_rst)
- for(k=0;k<4;k=k+1)
- rd_src[k] <= 7;
- else
- for(k=0;k<4;k=k+1)
- for(j=0;j<8;j=j+1)
- if(changed[j] & read_go[j] & (read_port[j]==k))
- rd_src[k] <= j;
-
mux8 #(.WIDTH(1))
- mux8_rd_ready0(.sel(rd_src[0]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+ mux8_rd_ready0(.en(~read_src[0][3]),.sel(read_src[0][2:0]),
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
.i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
.i5(rd_ready_o[5]), .i6(rd_ready_o[6]),
.i7(rd_ready_o[7]),.o(rd0_ready_o));
-
+
mux8 #(.WIDTH(1))
- mux8_rd_empty0(.sel(rd_src[0]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+ mux8_rd_empty0(.en(~read_src[0][3]),.sel(read_src[0][2:0]),
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
.i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
.i5(rd_empty_o[5]), .i6(rd_empty_o[6]),
.i7(rd_empty_o[7]),.o(rd0_empty_o));
mux8 #(.WIDTH(32))
- mux8_rd_dat_0 (.sel(rd_src[0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+ mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]),
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
.i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
.i5(rd_dat_o[5]), .i6(rd_dat_o[6]),
.i7(rd_dat_o[7]),.o(rd0_dat_o));
mux8 #(.WIDTH(1))
- mux8_rd_ready1(.sel(rd_src[1]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+ mux8_rd_ready1(.en(~read_src[1][3]),.sel(read_src[1][2:0]),
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
.i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
.i5(rd_ready_o[5]), .i6(rd_ready_o[6]),
.i7(rd_ready_o[7]),.o(rd1_ready_o));
mux8 #(.WIDTH(1))
- mux8_rd_empty1(.sel(rd_src[1]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+ mux8_rd_empty1(.en(~read_src[1][3]),.sel(read_src[1][2:0]),
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
.i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
.i5(rd_empty_o[5]), .i6(rd_empty_o[6]),
.i7(rd_empty_o[7]),.o(rd1_empty_o));
mux8 #(.WIDTH(32))
- mux8_rd_dat_1 (.sel(rd_src[1]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+ mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]),
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
.i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
.i5(rd_dat_o[5]), .i6(rd_dat_o[6]),
.i7(rd_dat_o[7]),.o(rd1_dat_o));
mux8 #(.WIDTH(1))
- mux8_rd_ready2(.sel(rd_src[2]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+ mux8_rd_ready2(.en(~read_src[2][3]),.sel(read_src[2][2:0]),
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
.i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
.i5(rd_ready_o[5]), .i6(rd_ready_o[6]),
.i7(rd_ready_o[7]),.o(rd2_ready_o));
mux8 #(.WIDTH(1))
- mux8_rd_empty2(.sel(rd_src[2]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+ mux8_rd_empty2(.en(~read_src[2][3]),.sel(read_src[2][2:0]),
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
.i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
.i5(rd_empty_o[5]), .i6(rd_empty_o[6]),
.i7(rd_empty_o[7]),.o(rd2_empty_o));
mux8 #(.WIDTH(32))
- mux8_rd_dat_2 (.sel(rd_src[2]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+ mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]),
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
.i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
.i5(rd_dat_o[5]), .i6(rd_dat_o[6]),
.i7(rd_dat_o[7]),.o(rd2_dat_o));
mux8 #(.WIDTH(1))
- mux8_rd_ready3(.sel(rd_src[3]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+ mux8_rd_ready3(.en(~read_src[3][3]),.sel(read_src[3][2:0]),
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
.i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
.i5(rd_ready_o[5]), .i6(rd_ready_o[6]),
.i7(rd_ready_o[7]),.o(rd3_ready_o));
mux8 #(.WIDTH(1))
- mux8_rd_empty3(.sel(rd_src[3]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+ mux8_rd_empty3(.en(~read_src[3][3]),.sel(read_src[3][2:0]),
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
.i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
.i5(rd_empty_o[5]), .i6(rd_empty_o[6]),
.i7(rd_empty_o[7]),.o(rd3_empty_o));
mux8 #(.WIDTH(32))
- mux8_rd_dat_3 (.sel(rd_src[3]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+ mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]),
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
.i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
.i5(rd_dat_o[5]), .i6(rd_dat_o[6]),
.i7(rd_dat_o[7]),.o(rd3_dat_o));
Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
2007-07-11 20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
2007-07-11 20:19:26 UTC (rev 5938)
@@ -1,58 +1,75 @@
-
// FIFO Interface to the 2K buffer RAMs
+// Read port is read-acknowledge
+// FIXME do we want to be able to interleave reads and writes?
module fifo_int
- (// Control Interface
- input clk,
- input rst,
- input [8:0] firstline,
- input [8:0] lastline,
- input [3:0] step,
- input read_go,
- input write_go,
- input clear,
- output done,
- output error,
+ #(parameter BUFF_NUM = 0)
+ (// Control Interface
+ input clk,
+ input rst,
+ input [31:0] ctrl_word,
+ input go,
+ output done,
+ output error,
+
+ // Buffer Interface
+ output en_o,
+ output we_o,
+ output reg [8:0] addr_o,
+ output [31:0] dat_to_buf,
+ input [31:0] dat_from_buf,
+
+ // Write FIFO Interface
+ input [31:0] wr_dat_i,
+ input wr_write_i,
+ input wr_done_i,
+ input wr_error_i,
+ output wr_ready_o,
+ output wr_full_o,
+
+ // Read FIFO Interface
+ output [31:0] rd_dat_o,
+ input rd_read_i,
+ input rd_done_i,
+ input rd_error_i,
+ output rd_ready_o,
+ output rd_empty_o
+ );
- // Buffer Interface
- output en_o,
- output we_o,
- output reg [8:0] addr_o,
- output [31:0] dat_to_buf,
- input [31:0] dat_from_buf,
-
- // Write FIFO Interface
- input [31:0] wr_dat_i,
- input wr_write_i,
- input wr_done_i,
- input wr_error_i,
- output wr_ready_o,
- output wr_full_o,
+ reg [31:0] ctrl_reg;
+ reg go_reg;
- // Read FIFO Interface
- output [31:0] rd_dat_o,
- input rd_read_i,
- input rd_done_i,
- input rd_error_i,
- output rd_ready_o,
- output rd_empty_o
- );
+ always @(posedge clk)
+ go_reg <= go;
- // FIXME do we want to be able to interleave reads and writes?
- // FIXME do we want rd_ack or rd_req?
+ always @(posedge clk)
+ if(rst)
+ ctrl_reg <= 0;
+ else
+ if(go & (ctrl_word[31:28] == BUFF_NUM))
+ ctrl_reg <= ctrl_word;
- wire rd_en, wr_en;
+ wire [8:0] firstline = ctrl_reg[8:0];
+ wire [8:0] lastline = ctrl_reg[17:9];
+ wire [3:0] step = ctrl_reg[21:18];
+ wire read = ctrl_reg[22];
+ wire write = ctrl_reg[23];
+ wire clear = ctrl_reg[24];
+ wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block
+ wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ?
- assign dat_to_buf = wr_dat_i;
- assign rd_dat_o = dat_from_buf;
-
+ wire rd_en, wr_en;
+
+ assign dat_to_buf = wr_dat_i;
+ assign rd_dat_o = dat_from_buf;
+
localparam IDLE = 3'd0;
localparam PRE_READ = 3'd1;
localparam READING = 3'd2;
localparam WRITING = 3'd3;
localparam ERROR = 3'd4;
-
+
reg [2:0] state;
always @(posedge clk)
@@ -67,12 +84,12 @@
else
case(state)
IDLE :
- if(read_go)
+ if(go_reg & read)
begin
addr_o <= firstline;
state <= PRE_READ;
end
- else if(write_go)
+ else if(go_reg & write)
begin
addr_o <= firstline;
state <= WRITING;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/mux4.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/mux4.v 2007-07-11
20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/control_lib/mux4.v 2007-07-11
20:19:26 UTC (rev 5938)
@@ -1,14 +1,16 @@
module mux4
- #(parameter WIDTH=32)
- (input [1:0] sel,
+ #(parameter WIDTH=32, parameter DISABLED=0)
+ (input en,
+ input [1:0] sel,
input [WIDTH-1:0] i0,
input [WIDTH-1:0] i1,
input [WIDTH-1:0] i2,
input [WIDTH-1:0] i3,
output [WIDTH-1:0] o);
- assign o = sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0);
+ assign o = en ? (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 :
i0)) :
+ DISABLED;
endmodule // mux4
Modified: gnuradio/branches/developers/matt/u2f/control_lib/mux8.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/mux8.v 2007-07-11
20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/control_lib/mux8.v 2007-07-11
20:19:26 UTC (rev 5938)
@@ -1,8 +1,9 @@
module mux8
- #(parameter WIDTH=32)
- (input [2:0] sel,
+ #(parameter WIDTH=32, parameter DISABLED=0)
+ (input en,
+ input [2:0] sel,
input [WIDTH-1:0] i0,
input [WIDTH-1:0] i1,
input [WIDTH-1:0] i2,
@@ -13,7 +14,8 @@
input [WIDTH-1:0] i7,
output [WIDTH-1:0] o);
- assign o = sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) : (sel[0] ?
i5 : i4)) :
- (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0));
+ assign o = en ? (sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) :
(sel[0] ? i5 : i4)) :
+ (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 :
i0))) :
+ DISABLED;
endmodule // mux8
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-07-11 20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-07-11 20:19:26 UTC (rev 5938)
@@ -26,10 +26,12 @@
wire read_tx, done_tx, error_tx, ready_tx, empty_tx;
reg [8:0] fl_tx, ll_tx;
- reg read_go_tx, write_go_tx, clear_tx;
+ reg tx_go, clear_tx;
wire fdone_tx, ferror_tx;
reg even;
+
+ reg [31:0] tx_ctrl_word, rx_ctrl_word;
serdes_tx serdes_tx
(.clk(clk),.rst(rst),
@@ -42,10 +44,10 @@
ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx),
.clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx));
- fifo_int fifo_int_tx
+ fifo_int #(.BUFF_NUM(1)) fifo_int_tx
(.clk(clk),.rst(rst),
-
.firstline(fl_tx),.lastline(ll_tx),.step(1),.read_go(read_go_tx),.write_go(write_go_tx),
- .clear(clear_tx),.done(fdone_tx),.error(ferror_tx),
+ .ctrl_word(tx_ctrl_word),.go(tx_go),
+ .done(fdone_tx),.error(ferror_tx),
.en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx),
@@ -65,7 +67,7 @@
wire write_rx, done_rx, error_rx, ready_rx, empty_rx;
reg [8:0] fl_rx, ll_rx;
- reg read_go_rx, write_go_rx, clear_rx;
+ reg rx_go, clear_rx;
wire fdone_rx, ferror_rx;
serdes_rx serdes_rx
@@ -79,10 +81,10 @@
ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx),
.clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx));
- fifo_int fifo_int_rx
+ fifo_int #(.BUFF_NUM(0)) fifo_int_rx
(.clk(clk),.rst(rst),
-
.firstline(fl_rx),.lastline(ll_rx),.step(1),.read_go(read_go_rx),.write_go(write_go_rx),
- .clear(clear_rx),.done(fdone_rx),.error(ferror_rx),
+ .ctrl_word(rx_ctrl_word),.go(rx_go),
+ .done(fdone_rx),.error(ferror_rx),
.en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx),
@@ -103,6 +105,8 @@
initial wb_en_rx <= 0;
initial begin
+ tx_go <= 0;
+ rx_go <= 0;
wb_adr <= 0;
wb_en_tx <=0;
wb_we <= 0;
@@ -125,16 +129,18 @@
even <= 0;
repeat(10)
@(posedge clk);
- write_go_rx <= 1;
+ rx_go <= 1;
+ rx_ctrl_word <= {4'b0,3'b0,1'b0,1'b1,1'b0,4'b1,9'd200,9'd10};
$display("Send write_go");
@(posedge clk);
- write_go_rx <= 0;
+ rx_go <= 0;
repeat(30)
@(posedge clk);
- read_go_tx = 1;
+ tx_ctrl_word <= {4'b1,3'b0,1'b0,1'b0,1'b1,4'b1,9'd100,9'd0};
+ tx_go = 1;
$display("Send read_go");
@(posedge clk);
- read_go_tx = 0;
+ tx_go = 0;
@(posedge clk);
@(posedge fdone_rx);
@(posedge clk);
@@ -143,35 +149,35 @@
even <= 1;
@(posedge clk);
@(posedge clk);
- write_go_rx <= 1;
+ rx_ctrl_word <= {4'b0,3'b0,1'b0,1'b1,1'b0,4'b1,9'd300,9'd120};
+ rx_go <= 1;
@(posedge clk);
- write_go_rx <= 0;
+ rx_go <= 0;
@(posedge clk);
- read_go_tx <= 1;
+ tx_ctrl_word <= {4'b1,3'b0,1'b0,1'b0,1'b1,4'b1,9'd400,9'd300};
+ tx_go <= 1;
@(posedge clk);
- read_go_tx <= 0;
+ tx_go <= 0;
@(posedge clk);
@(posedge fdone_rx);
$display("Got second packet (even)");
repeat(10)
@(posedge clk);
+ wb_adr <= 0;
+ repeat(511) begin
+ @(posedge clk);
+ wb_we <= 0;
+ wb_en_rx <= 1;
+ @(posedge clk);
+ wb_we <= 0;
+ wb_en_rx <= 0;
+ @(posedge clk);
+ $display("Addr %d\tData %h",wb_adr,wb_dat_o_rx);
+ wb_adr <= wb_adr + 1;
+ end // repeat (511)
$finish;
end // initial begin
- initial begin
- fl_tx = 0;
- fl_rx = 0;
- ll_tx = 100;
- ll_rx = 100;
- clear_tx = 0;
- clear_rx = 0;
- read_go_tx = 0;
- write_go_tx = 0;
- read_go_rx = 0;
- write_go_rx = 0;
- end
-
-
always @(posedge clk)
if(write_rx)
$display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx,
ready_rx, full_rx);
Modified: gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
2007-07-11 20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.c
2007-07-11 20:19:26 UTC (rev 5938)
@@ -3,19 +3,25 @@
void
clear_buf(int bufnum) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE + (bufnum<<2));
- *addr = 1<<28;
+ volatile int *addr = (int *)BUFFER_POOL_BASE;
+ *addr = (bufnum << 28) | (4<<25) | (1<<24); // disable port connections to
this buffer, clear state
}
void
-receive_to_buf(int bufnum, int step, int port, int fl, int ll) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE + (bufnum<<2));
- *addr = (port << 24) | (1<<23) | (step<<18) | (ll<<9) | fl;
+diable_port(int portnum) {
+ volatile int *addr = (int *)(BUFFER_POOL_BASE);
+ *addr = (8 << 28) | (portnum<<25); // disable buffer connections to this port
}
void
-send_from_buf(int bufnum, int step, int port, int fl, int ll) {
- volatile int *addr = (int *)(BUFFER_POOL_BASE + (bufnum<<2));
- *addr = (port << 26) | (1<<22) | (step<<18) | (ll<<9) | fl;
+receive_to_buf(int bufnum, int port, int step, int fl, int ll) {
+ volatile int *addr = (int *)(BUFFER_POOL_BASE);
+ *addr = (bufnum<<28) | (port << 25) | (1<<23) | (step<<18) | (ll<<9) | fl;
}
+void
+send_from_buf(int bufnum, int port, int step, int fl, int ll) {
+ volatile int *addr = (int *)(BUFFER_POOL_BASE);
+ *addr = (bufnum<<28) | (port << 25) | (1<<22) | (step<<18) | (ll<<9) | fl;
+}
+
Modified: gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
2007-07-11 20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/firmware/buffer_pool.h
2007-07-11 20:19:26 UTC (rev 5938)
@@ -1,5 +1,6 @@
// Buffer Pool Management
void clear_buf(int bufnum);
-void receive_to_buf(int bufnum, int step, int port, int fl, int ll);
-void send_from_buf(int bufnum, int step, int port, int fl, int ll);
+void disable_port(int portnum);
+void receive_to_buf(int bufnum, int port, int step, int fl, int ll);
+void send_from_buf(int bufnum, int port, int step, int fl, int ll);
Modified: gnuradio/branches/developers/matt/u2f/firmware/test1_main.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/test1_main.c 2007-07-11
20:13:58 UTC (rev 5937)
+++ gnuradio/branches/developers/matt/u2f/firmware/test1_main.c 2007-07-11
20:19:26 UTC (rev 5938)
@@ -41,12 +41,12 @@
sim_puts("Filled buffer 1\n");
- // rx SERDES into buffer #2 (buf,step,port,fl,ll)
- receive_to_buf(2, 1 , 0 , 10 , 300);
+ // rx SERDES into buffer #2 (buf,port,step,fl,ll)
+ receive_to_buf(2, 0, 1, 10, 300);
sim_puts("SERDES RX buffer setup\n");
- // send SERDES from buffer #0
- send_from_buf(0 /*buf#*/, 1 /*step*/, 0 /*port*/, 10 /*fl*/, 200 /*ll*/);
+ // send SERDES from buffer #0 (buf,port,step,fl,ll)
+ send_from_buf(0, 0, 1, 20, 200);
sim_puts("SERDES TX buffer setup\n");
// Set up TX Chain
@@ -56,7 +56,7 @@
dsp_tx_regs->interp_rate = 32;
// send to DACs from buffer #1
- send_from_buf(1 /*buf#*/, 1 /*step*/, 1 /*port*/, 20 /*fl*/, 200 /*ll*/);
+ send_from_buf(1 /*buf#*/, 1 /*port*/, 1 /*step*/, 20 /*fl*/, 250 /*ll*/);
sim_puts("DAC Buffer setup\n");
dsp_tx_regs->run_tx = 1;
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- [Commit-gnuradio] r5938 - in gnuradio/branches/developers/matt/u2f: control_lib firmware,
matt <=