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[Commit-gnuradio] r5579 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r5579 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS |
|
Date: |
Wed, 30 May 2007 22:18:53 -0600 (MDT) |
Author: matt
Date: 2007-05-30 22:18:53 -0600 (Wed, 30 May 2007)
New Revision: 5579
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
Log:
latest opencores CVS -- includes interrupts now!
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,9 +1,9 @@
/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
/aeMB_wbbus.v/1.1/Tue May 8 20:32:13 2007//
-/aeMB_aslu.v/1.9/Fri May 18 03:56:49 2007//
-/aeMB_control.v/1.6/Fri May 18 03:56:50 2007//
-/aeMB_core.v/1.6/Fri May 18 03:56:50 2007//
-/aeMB_decode.v/1.9/Fri May 18 03:56:50 2007//
-/aeMB_fetch.v/1.5/Fri May 18 03:56:50 2007//
-/aeMB_regfile.v/1.17/Fri May 18 03:56:50 2007//
+/aeMB_aslu.v/1.10/Thu May 31 04:09:13 2007//
+/aeMB_control.v/1.7/Thu May 31 04:09:13 2007//
+/aeMB_core.v/1.7/Thu May 31 04:09:13 2007//
+/aeMB_decode.v/1.10/Thu May 31 04:09:13 2007//
+/aeMB_fetch.v/1.6/Thu May 31 04:09:13 2007//
+/aeMB_regfile.v/1.18/Thu May 31 04:09:13 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.9 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.10 2007/05/30 18:44:30 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.10 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.9 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -58,10 +61,10 @@
module aeMB_aslu (/*AUTOARG*/
// Outputs
- dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
+ dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL, rMSR_IE,
// Inputs
sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
- rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, prst, drun, prun
+ rOPC, rPC, rIMM, rRD, rRA, rMXLDST, rFSM, nclk, prst, drun, prun
);
parameter DSIZ = 32;
@@ -70,6 +73,8 @@
output [31:0] rRESULT;
output [3:0] rDWBSEL;
+ output rMSR_IE;
+
input [31:0] sDWBDAT;
input rBRA, rDLY;
input [31:0] rREGA, rREGB;
@@ -81,6 +86,7 @@
input [15:0] rIMM;
input [4:0] rRD, rRA;
input [1:0] rMXLDST;
+ input [1:0] rFSM;
input nclk, prst, drun, prun;
@@ -173,7 +179,6 @@
Performs shift instructions as well as sign extension. This is
done in parallel with the other operations.
*/
-
wire wSRAC, wSRCC, wSRLC, wRES_SC;
wire [31:0] wSRA,wSRC, wSRL, wSEXT8, wSEXT16, wRES_S;
assign {wSRAC,wSRA} = {wOPA[0],wOPA[0],wOPA[31:1]};
@@ -201,9 +206,13 @@
done in parallel with other operations.
*/
+ wire [31:0] wMSR = {rMSR_C, 23'hae33, 5'b0, rMSR_C, rMSR_IE,
1'b0};
+ wire fMFS = (rOPC == 6'o45) & !rIMM[14];
reg [31:0] rRES_M;
- always @(/*AUTOSENSE*/rRA or wOPA or wOPB)
- rRES_M <= #1 (rRA[3]) ? wOPB : wOPA;
+ always @(/*AUTOSENSE*/fMFS or rRA or wMSR or wOPA or wOPB)
+ rRES_M <= (fMFS) ? wMSR :
+ (rRA[3]) ? wOPB :
+ wOPA;
/**
Data WISHBONE Bus
@@ -233,16 +242,40 @@
endcase // case (wADD[1:0])
/**
- RESULT + C
- ----------
+ STATUS REGISTER
+ ---------------
+
+ FIXME: rMSR[C] might need to be blocked (drun) during a branch.
+ TODO: MTS/MFS instruction
+ */
+
+ reg rMSR_IE, xMSR_IE;
+ wire fMTS = (rOPC == 6'o45) & rIMM[14];
+ always @(/*AUTOSENSE*/fMTS or rMSR_C or rMXALU or rOPC or rRES_AC
+ or rRES_SC or wOPA)
+ case (rMXALU)
+ 2'o0: xMSR_C <= #1 (rOPC[2]) ? rMSR_C : rRES_AC;
+ 2'o2: xMSR_C <= #1 rRES_SC;
+ 2'o1: xMSR_C <= #1 (fMTS) ? wOPA[2] : rMSR_C;
+ default: xMSR_C <= #1 rMSR_C;
+ endcase // case (rMXALU)
+
+ wire fRTID = (rOPC == 6'o55) & rRD[0];
+ always @(/*AUTOSENSE*/fMTS or fRTID or rFSM or rMSR_IE or wOPA) begin
+ xMSR_IE <= (rFSM == 2'o1) ? 1'b0 :
+ (fRTID) ? 1'b1 :
+ (fMTS) ? wOPA[1] :
+ rMSR_IE;
+ end
+
+ /**
+ RESULT
+ ------
The RESULT and MSR[C] are collected at the end of the pipeline,
depending on the operation selected. This was done in order to
- allow the operations to proceed in parallel for faster speed.
-
- FIXME: rMSR[C] might need to be blocked (drun) during a branch.
- TODO: MTS/MFS instruction
+ allow the operations to proceed in parallel for faster speed.
*/
-
+
always @(/*AUTOSENSE*/rMXALU or rRES_A or rRES_L or rRES_M
or rRES_S) begin
case (rMXALU)
@@ -252,20 +285,12 @@
2'o3: xRESULT <= #1 rRES_M;
endcase // case (rMXALU)
end
-
- always @(/*AUTOSENSE*/rMSR_C or rMXALU or rOPC or rRES_AC
- or rRES_SC) begin
- case (rMXALU)
- 2'o0: xMSR_C <= #1 (rOPC[2]) ? rMSR_C : rRES_AC;
- 2'o2: xMSR_C <= #1 rRES_SC;
- default: xMSR_C <= #1 rMSR_C;
- endcase // case (rMXALU)
- end
-
+
// PIPELINE REGISTER //////////////////////////////////////////////////
always @(negedge nclk)
if (prst) begin
+ rMSR_IE <= 1'b1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSEL <= 4'h0;
@@ -275,6 +300,7 @@
end else if (prun) begin
rRESULT <= #1 xRESULT;
rMSR_C <= #1 xMSR_C;
+ rMSR_IE <= #1 xMSR_IE;
rDWBSEL <= #1 xDWBSEL;
end
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_control.v,v 1.6 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_control.v,v 1.7 2007/05/30 18:44:30 sybreon Exp $
*
* AE68 System Control Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_control.v,v $
+ * Revision 1.7 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.6 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -51,7 +54,7 @@
rFSM, nclk, prst, prun, frun, drun,
// Inputs
sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
- rDWBSTB, dwb_ack_i, rBRA, rDLY
+ rDWBSTB, dwb_ack_i, rBRA, rDLY, iwb_dat_i, rMSR_IE
);
// System
input sys_rst_i, sys_clk_i;
@@ -67,7 +70,10 @@
input dwb_ack_i;
// Internal
- input rBRA, rDLY;
+ input rBRA, rDLY;
+ input [31:0] iwb_dat_i;
+ input rMSR_IE;
+
output [1:0] rFSM;
//, rLDST;
output nclk, prst, prun;
@@ -79,7 +85,7 @@
This master run signal will pause or run the entire pipeline. It
will pause for any incomplete bus transaction.
*/
-
+
assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
/**
@@ -87,9 +93,11 @@
--------
The following external signals are debounced and synchronised:
- Interrupt
+
+ TODO: Exceptions
*/
-
- reg [2:0] rEXC, rINT;
+ wire fINT;
+ reg [2:0] rEXC, rINT;
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
@@ -108,7 +116,7 @@
exception and software exceptions. Only interrupts are
implemented.
- TODO: Implement exceptions.
+ TODO: Implement Exceptions
*/
parameter [1:0]
FSM_RUN = 2'o0,
@@ -127,28 +135,64 @@
rFSM <= #1 rNXT;
end
- always @(/*AUTOSENSE*/rFSM or rINT)
+ always @(/*AUTOSENSE*/fINT or rFSM)
case (rFSM)
FSM_HWEXC: rNXT <= FSM_RUN;
//FSM_SWEXC: rNXT <= FSM_RUN;
FSM_HWINT: rNXT <= FSM_RUN;
default: begin
rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
- (rINT == 3'h3) ? FSM_HWINT :
+ (fINT) ? FSM_HWINT :
FSM_RUN;
end
endcase // case (rFSM)
+
+ /**
+ Interrupt Check
+ ---------------
+ It checks to make sure that all the instructions in the pipeline
+ are atomic before allowing the detection of interrupts. Empirical
+ response latency is 3-7 cycles.
+ */
+
+ wire [5:0] rOPC = iwb_dat_i[31:26];
+ reg [2:0] rHWINT;
+ reg [1:0] rNCLR;
+ wire fCLR = ~|rNCLR;
+ wire fNCLR = ({rOPC[5:4],rOPC[2:1]} == 4'b1011) | (rOPC == 6'o54) |
(rOPC == 6'o55);
+ assign fINT = (rHWINT == 3'o3) & fCLR;
+
+ always @(negedge nclk)
+ if (prst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rHWINT <= 3'h0;
+ // End of automatics
+ end else if (fINT) begin
+ rHWINT <= 3'o0;
+ end else if (prun & fCLR & rMSR_IE) begin
+ rHWINT <= {rHWINT[1:0],sys_int_i};
+ end
+
+ always @(negedge nclk)
+ if (prst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rNCLR <= 2'h0;
+ // End of automatics
+ end else if (prun) begin
+ rNCLR <= {rNCLR[0], fNCLR};
+ end
/**
Bubble
------
Pipeline bubbles are introduced during a branch or interrupt.
-
- TODO: Implement interrupt bubble.
*/
-
+
reg [1:0] rRUN, xRUN;
- assign {drun,frun} = xRUN;
+ wire fXCE = ~|rFSM;
+ assign {drun,frun} = {xRUN[1] & fXCE , xRUN[0] & fXCE};
always @(/*AUTOSENSE*/rBRA or rDLY) begin
xRUN <= {~(rBRA ^ rDLY), ~rBRA};
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_core.v,v 1.6 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_core.v,v 1.7 2007/05/30 18:44:30 sybreon Exp $
*
* AEMB 32-bit Microblaze Compatible Core
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -26,6 +26,9 @@
*
* HISTORY
* $Log: aeMB_core.v,v $
+ * Revision 1.7 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.6 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -98,6 +101,7 @@
wire [15:0] rIMM; // From decode of aeMB_decode.v
wire rIWBSTB; // From fetch of
aeMB_fetch.v
wire rLNK; // From decode of
aeMB_decode.v
+ wire rMSR_IE; // From aslu of
aeMB_aslu.v
wire [1:0] rMXALU; // From decode of aeMB_decode.v
wire [1:0] rMXLDST; // From decode of aeMB_decode.v
wire [1:0] rMXSRC; // From decode of aeMB_decode.v
@@ -178,7 +182,9 @@
.rDWBSTB (rDWBSTB),
.dwb_ack_i (dwb_ack_i),
.rBRA (rBRA),
- .rDLY (rDLY));
+ .rDLY (rDLY),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .rMSR_IE (rMSR_IE));
aeMB_aslu #(DSIZ)
aslu (/*AUTOINST*/
@@ -187,6 +193,7 @@
.dwb_sel_o (dwb_sel_o[3:0]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
+ .rMSR_IE (rMSR_IE),
// Inputs
.sDWBDAT (sDWBDAT[31:0]),
.rBRA (rBRA),
@@ -203,6 +210,7 @@
.rRD (rRD[4:0]),
.rRA (rRA[4:0]),
.rMXLDST (rMXLDST[1:0]),
+ .rFSM (rFSM[1:0]),
.nclk (nclk),
.prst (prst),
.drun (drun),
@@ -234,6 +242,7 @@
.rDWBSEL (rDWBSEL[3:0]),
.rREGA (rREGA[31:0]),
.rRESULT (rRESULT[31:0]),
+ .rFSM (rFSM[1:0]),
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
.prst (prst),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.9 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.10 2007/05/30 18:44:30 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.10 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.9 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -60,8 +63,8 @@
rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rOPC, rIMM, rDWBSTB,
rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, dwb_stb_o, dwb_we_o,
// Inputs
- sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, prst, drun,
- frun, prun
+ sDWBDAT, rDWBSEL, rREGA, rRESULT, rFSM, iwb_dat_i, nclk, prst,
+ drun, frun, prun
);
// Internal I/F
output [31:0] rSIMM;
@@ -76,6 +79,7 @@
input [31:0] sDWBDAT;
input [3:0] rDWBSEL;
input [31:0] rREGA, rRESULT;
+ input [1:0] rFSM;
// External I/F
input [31:0] iwb_dat_i;
@@ -126,7 +130,7 @@
xRB <= wRB;
xIMM <= wIMM;
end else begin
- xOPC <= 6'o40;
+ xOPC <= 6'o44;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xIMM <= 16'h0;
@@ -191,11 +195,11 @@
*/
reg [1:0] rMXALU, xMXALU;
- always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT) begin // frun
+ always @(/*AUTOSENSE*/fBRA or fLOGIC or fMISC or fSHIFT) begin // frun
xMXALU <= //(!fNBR) ? 2'o0 :
(fSHIFT) ? 2'o2 :
(fLOGIC) ? 2'o1 :
- (fBRA) ? 2'o3 :
+ (fBRA|fMISC) ? 2'o3 :
2'o0;
end
@@ -246,6 +250,7 @@
xMXLDST <= //(!fNBR) ? 2'o0 :
(fLD) ? 2'o2 :
(fST) ? 2'o3 :
+ //(fMISC) ? 2'o1 :
2'o0;
end else begin
/*UTORESET*/
@@ -339,7 +344,7 @@
This controls the generation of the BRANCH, DELAY and LINK
signals.
*/
-
+ wire fXCE = |rFSM;
reg rBRA, rDLY, rLNK, xBRA, xDLY, xLNK;
always @(/*AUTOSENSE*/drun or rBCC or rMXBRA or rMXDLY or rMXLNK)
if (drun) begin
@@ -402,10 +407,10 @@
assign dwb_stb_o = rDWBSTB;
assign dwb_we_o = rDWBWE;
- always @(/*AUTOSENSE*/drun or rMXLDST)
+ always @(/*AUTOSENSE*/drun or fXCE or rMXLDST)
if (drun) begin
- xDWBSTB <= rMXLDST[1];
- xDWBWE <= rMXLDST[0];
+ xDWBSTB <= rMXLDST[1] & !fXCE;
+ xDWBWE <= rMXLDST[0] & !fXCE;
end else begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_fetch.v,v 1.5 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_fetch.v,v 1.6 2007/05/30 18:44:30 sybreon Exp $
*
* AEMB Instruction Fetch
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_fetch.v,v $
+ * Revision 1.6 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.5 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -83,7 +86,7 @@
begin
// PC Sources - ALU, Direct, Next
case (rFSM)
- //2'b01: xIWBADR <= 32'h00000010; // HWINT
+ 2'b01: xIWBADR <= 32'h00000010; // HWINT
//2'b10: xIWBADR <= 32'h00000020; // HWEXC
//2'b11: xIWBADR <= #1 32'h00000008; // SWEXC
default: xIWBADR <= (rBRA) ? rRESULT : wPCNXT;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.17 2007/05/17 09:08:21 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.18 2007/05/30 18:44:30 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.18 2007/05/30 18:44:30 sybreon
+ * Added interrupt support.
+ *
* Revision 1.17 2007/05/17 09:08:21 sybreon
* Removed asynchronous reset signal.
*
@@ -121,10 +124,17 @@
reg [31:2] rPC_, xPC_;
reg [4:0] rRD_, xRD_;
+ reg rINT, xINT;
- always @(/*AUTOSENSE*/rPC or rRD) begin
- xPC_ <= rPC[31:2];
- xRD_ <= rRD;
+ always @(/*AUTOSENSE*/rFSM or rPC or rRD) begin
+ xPC_ <= rPC[31:2];
+ xINT <= (rFSM != 2'o0);
+
+ case (rFSM)
+ 2'o1: xRD_ <= 5'd14; // HWINT
+ //2'o2: xRD_ <= 5'd17; // HWEXC
+ default: xRD_ <= rRD;
+ endcase // case (rFSM)
end
/**
@@ -168,9 +178,10 @@
reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
- wire wDWE = (fLD | fLNK | fWE) & |rRD_ & prun;
- assign wDDAT = (fLD) ? sDWBDAT :
- (fLNK) ? {rPC_,2'd0} :
+ wire wDWE = (fLD | fLNK | fWE | rINT) & |rRD_ & prun;
+ assign wDDAT = (rINT|fLNK) ? {rPC_,2'd0} :
+ (fLD) ? sDWBDAT :
+ //(fLNK) ? {rPC_,2'd0} :
rRESULT;
assign rREGA = rMEMA[rRA];
@@ -227,13 +238,15 @@
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDAT <= 32'h0;
+ rINT <= 1'h0;
rPC_ <= 30'h0;
rRD_ <= 5'h0;
// End of automatics
end else if (prun) begin
rDWBDAT <= #1 xDWBDAT;
rPC_ <= xPC_;
- rRD_ <= xRD_;
+ rRD_ <= xRD_;
+ rINT <= xINT;
end
// SIMULATION ONLY ///////////////////////////////////////////////////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,3 +1,3 @@
/utestbench.v/1.1/Fri Apr 13 13:02:34 2007//
-/testbench.v/1.4/Mon Apr 30 17:31:54 2007//
+/testbench.v/1.5/Thu May 31 04:09:14 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-05-30 23:27:58 UTC (rev 5578)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-05-31 04:18:53 UTC (rev 5579)
@@ -1,5 +1,5 @@
/*
- * $Id: testbench.v,v 1.4 2007/04/30 15:56:50 sybreon Exp $
+ * $Id: testbench.v,v 1.5 2007/05/30 18:44:45 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: testbench.v,v $
+ * Revision 1.5 2007/05/30 18:44:45 sybreon
+ * Added interrupt support.
+ *
* Revision 1.4 2007/04/30 15:56:50 sybreon
* Removed byte acrobatics.
*
@@ -47,6 +50,9 @@
// INITIAL SETUP //////////////////////////////////////////////////////
reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+ reg svc;
+ integer inttime;
+
always #5 sys_clk_i = ~sys_clk_i;
initial begin
@@ -55,16 +61,19 @@
end
initial begin
+ inttime = ($random % 143 * 7) + 2000;
+ svc = 0;
sys_clk_i = 1;
sys_rst_i = 0;
sys_int_i = 0;
sys_exc_i = 0;
#10 sys_rst_i = 1;
- #10000 sys_int_i = 1;
- #100 sys_int_i = 0;
end
-
- initial fork
+
+ initial fork
+ //inttime $display("FSADFASDFSDAF");
+ //#1010 sys_int_i = 1;
+ //#1000 sys_int_i = 0;
//#100000 $displayh("\nTest Completed.");
//#11000 $finish;
join
@@ -120,31 +129,45 @@
end
// DISPLAY OUTPUTS ///////////////////////////////////////////////////
-
+
always @(negedge sys_clk_i) begin
-
- $write("\nT: ",$stime);
+
+ // Time
+ $write("\nT: ",($stime / 10));
+
+ // Data Monitors
if (iwb_stb_o & iwb_ack_i)
- $writeh("\tPC: 0x",iwb_adr_o,"=0x",iwb_dat_i);
+ $writeh("\t @",iwb_adr_o,":",iwb_dat_i);
if (dwb_stb_o & dwb_we_o & dwb_ack_i)
- $writeh("\tST: 0x",dwb_adr_o,"=0x",dwb_dat_o," S=0x",dwb_sel_o);
+ $writeh("\t @",dwb_adr_o,"<-",dwb_dat_o,"#",dwb_sel_o);
if (dwb_stb_o & ~dwb_we_o & dwb_ack_i)
- $writeh("\tLD: 0x",dwb_adr_o,"=0x",dwb_dat_i," S=0x",dwb_sel_o);
+ $writeh("\t @",dwb_adr_o,"->",dwb_dat_i,"#",dwb_sel_o);
if (dut.regfile.wDWE)
- $writeh("\tR",dut.regfile.rRD_,"=",dut.regfile.wDDAT,";");
-
- if (dwb_we_o & (dwb_dat_o == "INTR"))
- $display("\t*** SERVICE ***");
- if (dut.control.rFSM == 2'o1)
- $display("\t*** INTERRUPT ***");
-
+ $writeh("\t R",dut.regfile.rRD_,"=",dut.regfile.wDDAT,";");
+
+ // Interrupt Monitors
+ if ($stime > inttime) begin
+ sys_int_i = 1;
+ svc = 0;
+ end
+ if (($stime > inttime+500) && !svc) begin
+ $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
+ $finish;
+ end
+ if (dwb_we_o & (dwb_dat_o == "RTNI")) begin
+ sys_int_i = 0;
+ end
+ if (dut.control.rFSM == 2'o1) begin
+ $writeh("\tINTR: ",(($stime-inttime)/10), " cycles");
+ inttime = ($random % 181 * 11) + $stime + 5000;
+ svc = 1;
+ end
+
+ // Pass/Fail Monitors
if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
- $display("\tFAIL");
+ $display("\n\tFAIL");
$finish;
end
- if (dwb_we_o & (dwb_dat_o == "PASS")) begin
- $display("\tPASS");
- end
if (iwb_dat_i == 32'hb8000000) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
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- [Commit-gnuradio] r5579 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS,
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