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[Commit-gnuradio] r5495 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r5495 - in gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog: . CVS |
|
Date: |
Thu, 17 May 2007 22:04:22 -0600 (MDT) |
Author: matt
Date: 2007-05-17 22:04:21 -0600 (Thu, 17 May 2007)
New Revision: 5495
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
Log:
latest CVS from opencores, now has synchronous Reset
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,9 +1,9 @@
/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
-/aeMB_wbbus.v/1.1/Fri Apr 13 13:02:34 2007//
-/aeMB_control.v/1.4/Fri Apr 27 01:14:55 2007//
-/aeMB_core.v/1.5/Fri Apr 27 01:14:55 2007//
-/aeMB_fetch.v/1.4/Fri Apr 27 01:14:55 2007//
-/aeMB_aslu.v/1.8/Mon Apr 30 17:31:53 2007//
-/aeMB_decode.v/1.8/Mon Apr 30 17:31:54 2007//
-/aeMB_regfile.v/1.15/Mon Apr 30 17:31:54 2007//
+/aeMB_wbbus.v/1.1/Tue May 8 20:32:13 2007//
+/aeMB_aslu.v/1.9/Fri May 18 03:56:49 2007//
+/aeMB_control.v/1.6/Fri May 18 03:56:50 2007//
+/aeMB_core.v/1.6/Fri May 18 03:56:50 2007//
+/aeMB_decode.v/1.9/Fri May 18 03:56:50 2007//
+/aeMB_fetch.v/1.5/Fri May 18 03:56:50 2007//
+/aeMB_regfile.v/1.17/Fri May 18 03:56:50 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.8 2007/04/30 15:56:50 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.9 2007/05/17 09:08:21 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.9 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
* Revision 1.8 2007/04/30 15:56:50 sybreon
* Removed byte acrobatics.
*
@@ -58,7 +61,7 @@
dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
// Inputs
sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
- rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, nrun
+ rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, prst, drun, prun
);
parameter DSIZ = 32;
@@ -79,7 +82,7 @@
input [4:0] rRD, rRA;
input [1:0] rMXLDST;
- input nclk, nrst, drun, nrun;
+ input nclk, prst, drun, prun;
reg [31:0] rRESULT, xRESULT;
reg rMSR_C, xMSR_C;
@@ -261,15 +264,15 @@
// PIPELINE REGISTER //////////////////////////////////////////////////
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSEL <= 4'h0;
rMSR_C <= 1'h0;
rRESULT <= 32'h0;
// End of automatics
- end else if (nrun) begin
+ end else if (prun) begin
rRESULT <= #1 xRESULT;
rMSR_C <= #1 xMSR_C;
rDWBSEL <= #1 xDWBSEL;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_control.v,v 1.4 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_control.v,v 1.6 2007/05/17 09:08:21 sybreon Exp $
*
* AE68 System Control Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,12 @@
*
* HISTORY
* $Log: aeMB_control.v,v $
+ * Revision 1.6 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
+ * Revision 1.5 2007/05/16 12:32:21 sybreon
+ * Added async BRA/DLY signals for future clock, reset, and interrupt features.
+ *
* Revision 1.4 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -42,7 +48,7 @@
module aeMB_control (/*AUTOARG*/
// Outputs
- rFSM, nclk, nrst, nrun, frun, drun,
+ rFSM, nclk, prst, prun, frun, drun,
// Inputs
sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
rDWBSTB, dwb_ack_i, rBRA, rDLY
@@ -64,7 +70,7 @@
input rBRA, rDLY;
output [1:0] rFSM;
//, rLDST;
- output nclk, nrst, nrun;
+ output nclk, prst, prun;
output frun, drun;
/**
@@ -74,36 +80,23 @@
will pause for any incomplete bus transaction.
*/
- assign nrun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
+ assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
/**
Debounce
--------
The following external signals are debounced and synchronised:
- - Reset
- Interrupt
*/
- reg [1:0] rRST;
- always @(negedge nclk or negedge sys_rst_i)
- if (!sys_rst_i) begin
- //rNRST <= 2'h3;
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- rRST <= 2'h0;
- // End of automatics
- end else begin
- rRST <= {rRST[0],1'b1};
- end
-
reg [2:0] rEXC, rINT;
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rINT <= 3'h0;
// End of automatics
- end else if (nrun) begin
+ end else if (prun) begin
//rEXC <= #1 {rEXC[1:0], sys_exc_i};
rINT <= #1 {rINT[1:0], sys_int_i};
end
@@ -124,13 +117,13 @@
FSM_HWINT = 2'o1;
reg [1:0] rFSM, rNXT;
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rFSM <= 2'h0;
// End of automatics
- end else if (nrun) begin
+ end else if (prun) begin
rFSM <= #1 rNXT;
end
@@ -154,17 +147,13 @@
TODO: Implement interrupt bubble.
*/
- reg [1:0] rRUN;
- assign {drun,frun} = rRUN;
-
- always @(posedge nclk or negedge nrst)
- if (!nrst) begin
- rRUN <= 2'h3;
- /*AUTORESET*/
- end else begin
- rRUN <= #1 {~(rBRA ^ rDLY), ~rBRA};
- end
+ reg [1:0] rRUN, xRUN;
+ assign {drun,frun} = xRUN;
+ always @(/*AUTOSENSE*/rBRA or rDLY) begin
+ xRUN <= {~(rBRA ^ rDLY), ~rBRA};
+ end
+
/**
Clock/Reset
-----------
@@ -172,8 +161,17 @@
DCM/PLL/DPLL can be instantiated here if needed.
*/
+ reg [1:0] rRST;
assign nclk = sys_clk_i;
- assign nrst = rRST[1];
+ assign prst = rRST[1];
+ always @(negedge nclk)
+ if (!sys_rst_i) begin
+ rRST <= 2'h3;
+ /*AUTORESET*/
+ end else begin
+ rRST <= {rRST[0],1'b0};
+ end
+
endmodule // aeMB_control
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_core.v,v 1.5 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_core.v,v 1.6 2007/05/17 09:08:21 sybreon Exp $
*
* AEMB 32-bit Microblaze Compatible Core
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -26,6 +26,9 @@
*
* HISTORY
* $Log: aeMB_core.v,v $
+ * Revision 1.6 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
* Revision 1.5 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -84,8 +87,8 @@
wire drun; // From control of
aeMB_control.v
wire frun; // From control of
aeMB_control.v
wire nclk; // From control of
aeMB_control.v
- wire nrst; // From control of
aeMB_control.v
- wire nrun; // From control of
aeMB_control.v
+ wire prst; // From control of
aeMB_control.v
+ wire prun; // From control of
aeMB_control.v
wire rBRA; // From decode of
aeMB_decode.v
wire rDLY; // From decode of
aeMB_decode.v
wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
@@ -136,9 +139,9 @@
.rLNK (rLNK),
.rRWE (rRWE),
.nclk (nclk),
- .nrst (nrst),
+ .prst (prst),
.drun (drun),
- .nrun (nrun));
+ .prun (prun));
aeMB_fetch #(ISIZ)
fetch (/*AUTOINST*/
@@ -150,8 +153,8 @@
// Inputs
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
- .nrst (nrst),
- .nrun (nrun),
+ .prst (prst),
+ .prun (prun),
.rFSM (rFSM[1:0]),
.rBRA (rBRA),
.rRESULT (rRESULT[31:0]));
@@ -161,8 +164,8 @@
// Outputs
.rFSM (rFSM[1:0]),
.nclk (nclk),
- .nrst (nrst),
- .nrun (nrun),
+ .prst (prst),
+ .prun (prun),
.frun (frun),
.drun (drun),
// Inputs
@@ -201,9 +204,9 @@
.rRA (rRA[4:0]),
.rMXLDST (rMXLDST[1:0]),
.nclk (nclk),
- .nrst (nrst),
+ .prst (prst),
.drun (drun),
- .nrun (nrun));
+ .prun (prun));
aeMB_decode
decode (/*AUTOINST*/
@@ -233,9 +236,9 @@
.rRESULT (rRESULT[31:0]),
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
- .nrst (nrst),
+ .prst (prst),
.drun (drun),
.frun (frun),
- .nrun (nrun));
+ .prun (prun));
endmodule // aeMB_core
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.8 2007/04/30 15:58:31 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.9 2007/05/17 09:08:21 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.9 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
* Revision 1.8 2007/04/30 15:58:31 sybreon
* Fixed minor data hazard bug spotted by Matt Ettus.
*
@@ -57,8 +60,8 @@
rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rOPC, rIMM, rDWBSTB,
rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, dwb_stb_o, dwb_we_o,
// Inputs
- sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, nrst, drun,
- frun, nrun
+ sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, prst, drun,
+ frun, prun
);
// Internal I/F
output [31:0] rSIMM;
@@ -79,7 +82,7 @@
output dwb_stb_o, dwb_we_o;
// System I/F
- input nclk, nrst, drun, frun, nrun;
+ input nclk, prst, drun, frun, prun;
/**
rOPC/rRD/rRA/rRB/rIMM
@@ -106,6 +109,14 @@
reg [5:0] xOPC;
reg [4:0] xRD, xRA, xRB;
reg [15:0] xIMM;
+
+ /*
+ assign rOPC = wOPC;
+ assign rRA = wRA;
+ assign rRB = wRB;
+ assign rRD = wRD;
+ assign rIMM = wIMM;
+ */
always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
if (frun) begin
@@ -405,8 +416,8 @@
// PIPELINE REGISTERS ///////////////////////////////////////////////
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
//rOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
@@ -433,7 +444,7 @@
rRWE <= 1'h0;
rSIMM <= 32'h0;
// End of automatics
- end else if (nrun) begin // if (!nrst)
+ end else if (prun) begin // if (prst)
rIMM <= #1 xIMM;
rOPC <= #1 xOPC;
rRA <= #1 xRA;
@@ -460,7 +471,7 @@
rRWE <= #1 xRWE;
rDWBSTB <= #1 xDWBSTB;
rDWBWE <= #1 xDWBWE;
- end // if (nrun)
+ end // if (prun)
endmodule // aeMB_decode
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_fetch.v,v 1.4 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_fetch.v,v 1.5 2007/05/17 09:08:21 sybreon Exp $
*
* AEMB Instruction Fetch
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_fetch.v,v $
+ * Revision 1.5 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
* Revision 1.4 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -45,7 +48,7 @@
// Outputs
iwb_adr_o, iwb_stb_o, rPC, rIWBSTB,
// Inputs
- iwb_dat_i, nclk, nrst, nrun, rFSM, rBRA, rRESULT
+ iwb_dat_i, nclk, prst, prun, rFSM, rBRA, rRESULT
);
parameter ISIZ = 32;
@@ -55,7 +58,7 @@
input [31:0] iwb_dat_i;
// System
- input nclk, nrst, nrun;
+ input nclk, prst, prun;
// Internal
output [31:0] rPC;
@@ -91,14 +94,14 @@
// PIPELINE REGISTERS //////////////////////////////////////////////////
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rIWBADR <= 32'h0;
rPC <= 32'h0;
// End of automatics
- end else if (nrun) begin
+ end else if (prun) begin
rPC <= #1 xPC;
rIWBADR <= #1 xIWBADR;
end
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-05-18 03:56:21 UTC (rev 5494)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-05-18 04:04:21 UTC (rev 5495)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.15 2007/04/30 15:56:50 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.17 2007/05/17 09:08:21 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -27,6 +27,12 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.17 2007/05/17 09:08:21 sybreon
+ * Removed asynchronous reset signal.
+ *
+ * Revision 1.16 2007/05/15 22:44:57 sybreon
+ * Corrected speed issues after rev 1.9 update.
+ *
* Revision 1.15 2007/04/30 15:56:50 sybreon
* Removed byte acrobatics.
*
@@ -82,7 +88,7 @@
dwb_dat_o, rREGA, rREGB, sDWBDAT,
// Inputs
dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
- rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
+ rOPC, rDWBSEL, rLNK, rRWE, nclk, prst, drun, prun
);
// FIXME: This parameter is not used here.
parameter DSIZ = 32;
@@ -102,7 +108,7 @@
input [5:0] rOPC;
input [3:0] rDWBSEL;
input rLNK, rRWE;
- input nclk, nrst, drun, nrun;
+ input nclk, prst, drun, prun;
/**
Delay Latches
@@ -162,19 +168,17 @@
reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
- wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
+ wire wDWE = (fLD | fLNK | fWE) & |rRD_ & prun;
assign wDDAT = (fLD) ? sDWBDAT :
(fLNK) ? {rPC_,2'd0} :
rRESULT;
- assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
- assign wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
assign rREGA = rMEMA[rRA];
assign rREGB = rMEMB[rRB];
assign wREGD = rMEMD[rRD];
always @(negedge nclk)
- if (wDWE | !nrst) begin
+ if (wDWE | prst) begin
rMEMA[rRD_] <= wDDAT;
rMEMB[rRD_] <= wDDAT;
rMEMD[rRD_] <= wDDAT;
@@ -184,19 +188,23 @@
Memory Resizer
--------------
This moves the appropriate bytes around depending on the size of
- the operation. There is no checking for invalid size selection.
+ the operation. There is no checking for invalid size selection. It
+ also handles forwarding.
*/
- reg [31:0] sWBDAT;
- always @(/*AUTOSENSE*/rOPC or wWBDAT)
- case (rOPC[1:0])
+ reg [31:0] xDWBDAT;
+ always @(/*AUTOSENSE*/fDFWD or rOPC or rRESULT or wREGD)
+ case ({fDFWD,rOPC[1:0]})
// 8-bit
- 2'o0: sWBDAT <= {(4){wWBDAT[7:0]}};
+ 3'o0: xDWBDAT <= {(4){wREGD[7:0]}};
+ 3'o4: xDWBDAT <= {(4){rRESULT[7:0]}};
// 16-bit
- 2'o1: sWBDAT <= {(2){wWBDAT[15:0]}};
+ 3'o1: xDWBDAT <= {(2){wREGD[15:0]}};
+ 3'o5: xDWBDAT <= {(2){rRESULT[15:0]}};
// 32-bit
- default: sWBDAT <= wWBDAT;
- endcase // case (rOPC[1:0])
+ 3'o2, 3'o3: xDWBDAT <= wREGD;
+ 3'o6, 3'o7: xDWBDAT <= rRESULT;
+ endcase // case ({fDFWD,rOPC[1:0]})
always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
case (rDWBSEL)
@@ -214,16 +222,16 @@
// PIPELINE REGISTERS //////////////////////////////////////////////////
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
+ always @(negedge nclk)
+ if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDAT <= 32'h0;
rPC_ <= 30'h0;
rRD_ <= 5'h0;
// End of automatics
- end else if (nrun) begin
- rDWBDAT <= #1 sWBDAT;
+ end else if (prun) begin
+ rDWBDAT <= #1 xDWBDAT;
rPC_ <= xPC_;
rRD_ <= xRD_;
end
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- [Commit-gnuradio] r5495 - in gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog: . CVS,
matt <=