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[Commit-gnuradio] r5462 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5462 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
|
Date: |
Sat, 12 May 2007 18:34:54 -0600 (MDT) |
Author: thottelt
Date: 2007-05-12 18:34:54 -0600 (Sat, 12 May 2007)
New Revision: 5462
Added:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_inst.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
Log:
fix synthesis and small bugs found with fake_fx2
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -97,11 +97,12 @@
if (tx_strobe == 1)
tx_empty <= 1 ;
- //Check Start burst flag
- if (fifodata[3] == 1)
+ //Check Start/End burst flag
+ if (fifodata[3] == 1 && fifodata[4] == 1)
+ burst <= 0;
+ else if (fifodata[3] == 1)
burst <= 1;
-
- if (fifodata[4] == 1)
+ else if (fifodata[4] == 1)
burst <= 0;
payload_len <= (fifodata & 16'h1FF) ;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -32,7 +32,7 @@
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
- always @(usb_ram_ain, usb_ram_aout)
+ always @(usb_ram_ain, usb_ram_aout, reset)
begin
if (reset)
pkt_waiting <= 0;
@@ -45,72 +45,49 @@
end
// Check if there is room
- always @(usb_ram_ain, usb_ram_aout)
+ always @(usb_ram_ain, usb_ram_aout, reset)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
- have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH *
(NUM_PACKETS - 1))? 1 : 0;
+ have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH *
(NUM_PACKETS - 1))? 1'b1 : 1'b0;
else
have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
- /* RAM Write Address process */
+ /* RAM Writing/Reading process */
always @(posedge clock)
begin
- if( reset )
- begin
- usb_ram_offset_in <= 0 ;
- usb_ram_packet_in <= 0 ;
- end
- else
- if( pkt_complete )
- begin
- usb_ram_packet_in <= usb_ram_packet_in + 1;
-
- usb_ram_offset_in <= 0;
- if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
- isfull <= 1 ;
- end
- else if( write_enable )
- begin
- if (usb_ram_offset_in == 7'b1111111)
- begin
- usb_ram_offset_in <= 7'b1111111;
- end
- else
- usb_ram_offset_in <= usb_ram_offset_in + 1 ;
- end
- end
-
- /* RAM Writing process */
- always @(posedge clock)
- begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
+ ram_data_out <= usb_ram[usb_ram_aout] ;
end
- /* RAM Read Address process */
+ /* RAM Write/Read Address process */
always @(posedge clock)
begin
if( reset )
begin
usb_ram_packet_out <= 0 ;
usb_ram_offset_out <= 0 ;
+ usb_ram_offset_in <= 0 ;
+ usb_ram_packet_in <= 0 ;
isfull <= 0;
end
else
+ begin
if( skip_packet )
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
isfull <= 0;
end
- else if(read_enable) begin
+ else if(read_enable)
+ begin
if( usb_ram_offset_out == 7'b1111111 )
begin
isfull <= 0 ;
@@ -119,15 +96,22 @@
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
- end
- /*if (usb_ram_ain + 1 == usb_ram_aout)
- isfull <= 0; */
+ end
+ if( pkt_complete )
+ begin
+ usb_ram_packet_in <= usb_ram_packet_in + 1 ;
+ usb_ram_offset_in <= 0 ;
+ if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
+ isfull <= 1 ;
+ end
+ else if( write_enable )
+ begin
+ if (usb_ram_offset_in == 7'b1111111)
+ usb_ram_offset_in <= 7'b1111111 ;
+ else
+ usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+ end
+ end
end
- /* RAM Reading Process */
- always @(posedge clock)
- begin
- ram_data_out <= usb_ram[usb_ram_aout] ;
- end
-
endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -60,8 +60,8 @@
wire tupf_pkt_waiting ;
wire tupf_rdreq ;
wire tupf_write_enable ;
- wire tupf_wrfull ;
- wire [7:0] tupf_usedw ;
+ wire [7:0] tupf_rdusedw ;
+ wire [7:0] tupf_wrusedw ;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
@@ -76,8 +76,8 @@
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
- assign have_space = ~tupf_wrfull ;
- assign tupf_pkt_waiting = (tupf_usedw >= 128) ;
+ assign have_space = (tupf_wrusedw <= 128) ;
+ assign tupf_pkt_waiting = (tupf_rdusedw >= 128) ;
/* TODO: Figure out how to write this genericly */
assign tx_empty = txempty_chan[0] & txempty_chan[1] ;
@@ -86,12 +86,16 @@
assign tx_q_0 = txempty_chan[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = txempty_chan[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = txempty_chan[1] ? 16'b0 : tx_q[1] ;
-
-
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
+ assign tx_q_2 = 16'b0 ;
+ assign tx_i_2 = 16'b0 ;
+ assign tx_q_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign debugbus = 12'b0 ;
usb_fifo_writer tx_usb_packet_writer
( .reset (reset),
@@ -109,10 +113,11 @@
.data (tupf_fifodata_in),
.wrreq (tupf_write_enable),
.q (tupf_fifodata_out),
- .rdreq (tupf_rdreq),
- .wrfull (tupf_wrfull),
+ .rdreq (tupf_rdreq),
+ .wrfull (/* VOID */),
+ .wrusedw (tupf_wrusedw),
.rdempty (/* VOID */),
- .rdusedw (tupf_usedw)
+ .rdusedw (tupf_rdusedw)
);
usb_fifo_reader #(NUM_CHAN) tx_usb_packet_reader
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-05-13 00:34:54 UTC (rev 5462)
@@ -73,6 +73,13 @@
(line (pt 160 40)(pt 144 40)(line_width 1))
)
(port
+ (pt 160 72)
+ (output)
+ (text "wrusedw[7..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[7..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 3))
+ )
+ (port
(pt 160 96)
(output)
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
2007-05-13 00:34:54 UTC (rev 5462)
@@ -25,6 +25,7 @@
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- wrfull : OUT STD_LOGIC
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
2007-05-13 00:34:54 UTC (rev 5462)
@@ -27,5 +27,6 @@
q[31..0],
rdempty,
rdusedw[7..0],
- wrfull
+ wrfull,
+ wrusedw[7..0]
);
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-05-12 23:50:46 UTC (rev 5461)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -43,7 +43,8 @@
q,
rdempty,
rdusedw,
- wrfull);
+ wrfull,
+ wrusedw);
input aclr;
input [31:0] data;
@@ -55,15 +56,18 @@
output rdempty;
output [7:0] rdusedw;
output wrfull;
+ output [7:0] wrusedw;
wire sub_wire0;
- wire sub_wire1;
- wire [31:0] sub_wire2;
- wire [7:0] sub_wire3;
+ wire [7:0] sub_wire1;
+ wire sub_wire2;
+ wire [31:0] sub_wire3;
+ wire [7:0] sub_wire4;
wire rdempty = sub_wire0;
- wire wrfull = sub_wire1;
- wire [31:0] q = sub_wire2[31:0];
- wire [7:0] rdusedw = sub_wire3[7:0];
+ wire [7:0] wrusedw = sub_wire1[7:0];
+ wire wrfull = sub_wire2;
+ wire [31:0] q = sub_wire3[31:0];
+ wire [7:0] rdusedw = sub_wire4[7:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
@@ -73,13 +77,13 @@
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
- .wrfull (sub_wire1),
- .q (sub_wire2),
- .rdusedw (sub_wire3)
+ .wrusedw (sub_wire1),
+ .wrfull (sub_wire2),
+ .q (sub_wire3),
+ .rdusedw (sub_wire4)
// synopsys translate_off
,
.wrempty (),
- .wrusedw (),
.rdfull ()
// synopsys translate_on
);
@@ -130,7 +134,7 @@
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -153,6 +157,7 @@
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
@@ -162,6 +167,7 @@
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -38,7 +38,8 @@
q,
rdempty,
rdusedw,
- wrfull);
+ wrfull,
+ wrusedw);
input aclr;
input [31:0] data;
@@ -50,6 +51,7 @@
output rdempty;
output [7:0] rdusedw;
output wrfull;
+ output [7:0] wrusedw;
endmodule
@@ -83,7 +85,7 @@
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -106,6 +108,7 @@
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
@@ -115,6 +118,7 @@
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_inst.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_inst.v
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_inst.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -8,5 +8,6 @@
.q ( q_sig ),
.rdempty ( rdempty_sig ),
.rdusedw ( rdusedw_sig ),
- .wrfull ( wrfull_sig )
+ .wrfull ( wrfull_sig ),
+ .wrusedw ( wrusedw_sig )
);
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-05-12 23:50:46 UTC (rev 5461)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-05-13 00:34:54 UTC (rev 5462)
@@ -372,8 +372,10 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_writer.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v
Added:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-05-12 23:50:46 UTC (rev 5461)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -1,45 +1,88 @@
module fake_fx2();
integer file, start, count, r;
+
reg [15:0] packet [255:0];
reg usbclock;
+reg txclock;
reg reset;
reg [7:0] i;
reg [15:0] usbdata;
reg WR;
-reg [100:0]line;
-reg [7:0]x1;
-reg [7:0]x2;
-reg [7:0]x3;
-reg [7:0]x4;
-
wire have_space;
+wire txstrobe;
+wire tx_empty;
+wire tx_underrun;
+wire [15:0]tx_i_0;
+wire [15:0]tx_q_0;
+wire [15:0]tx_i_1;
+wire [15:0]tx_q_1;
+wire [15:0]tx_i_2;
+wire [15:0]tx_q_2;
+wire [15:0]tx_i_3;
+wire [15:0]tx_q_3;
-fake_fx2_test fake_tx_buffer(
- .usbdata(usbdata),
+/* NOT USED YET */
+reg bus_reset;
+reg clear_status;
+reg channels;
+
+tx_buffer_inband tx_buffer_inband_ (
.usbclk(usbclock),
.reset(reset),
+ .usbdata(usbdata),
+ .WR(WR),
+ .txclk(txclock),
+ .txstrobe(txstrobe),
+ .tx_empty(tx_empty),
.have_space(have_space),
- .WR(WR)
- );
+ .tx_underrun(tx_underrun),
+ .tx_i_0(tx_i_0),
+ .tx_i_1(tx_i_1),
+ .tx_i_2(tx_i_2),
+ .tx_i_3(tx_i_3),
+ .tx_q_0(tx_q_0),
+ .tx_q_1(tx_q_1),
+ .tx_q_2(tx_q_2),
+ .tx_q_3(tx_q_3),
+ .bus_reset(1'b0),
+ .clear_status(1'b0),
+ .channels(4'b0),
+ .debugbus()
+);
+strobe_gen strobe_gen_test(
+ .clock(txclock),
+ .reset(reset),
+ .enable(1'd1),
+ .rate(8'd3),
+ .strobe_in(1'd1),
+ .strobe(txstrobe) );
+
+
initial begin
- file = $fopen("packets.txt", "r");
+ file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ //file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
start = 0;
count = 0;
usbclock = 0;
+ txclock = 0;
WR = 0;
reset = 1;
i = 0;
+ bus_reset = 0;
+ clear_status = 0;
+ channels = 0;
+
#40 reset = 0;
if (file == 0)
- begin
- $display("cannot open packet.txt");
+ begin
+ $display("cannot open specified file");
$finish;
- end
+ end
while($feof(file) == 0)
begin
@@ -53,19 +96,23 @@
end
// Wait
+ i = 0;
while(have_space == 0)
begin
@(posedge usbclock)
i = 0;
end
- repeat (256) begin
+ repeat (256) begin
@(posedge usbclock)
WR = 1;
usbdata = packet[i];
i = i + 1 ;
end
- WR = 0;
+ @(posedge usbclock)
+ WR = 0;
+ @(posedge usbclock)
+ WR = 0;
end
$fclose(file);
@@ -73,5 +120,7 @@
always
#2 usbclock = ~ usbclock;
+always
+ #5 txclock = ~ txclock;
endmodule
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-12
23:50:46 UTC (rev 5461)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-13
00:34:54 UTC (rev 5462)
@@ -253,27 +253,27 @@
Project_File_3 = ./fake_fx2_test.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = ./fake_fx2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178480747 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015942 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178726590 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178648314 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179010971 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178727140 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015841 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = ./chan_fifo_readers_test.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178644650 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015567 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = ./usb_packet_fifo_test.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178644305 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = ./tx_buffer_test.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178725490 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015176 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = ./usb_fifo_reader_test.v
@@ -307,6 +307,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/usb_packet_fifo_test.v 0
1} {Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/simulations/fake_fx2.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-05-12 23:50:46 UTC (rev 5461)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-05-13 00:34:54 UTC (rev 5462)
@@ -52,7 +52,7 @@
.bus_reset(1'b0),
.clear_status(1'b0),
.channels(4'b0),
- .debugbus(debugbus)
+ .debugbus()
);
strobe_gen strobe_gen_test(
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- [Commit-gnuradio] r5462 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells inband/usrp/fpga/toplevel/usrp_inband_usb simulations,
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