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[Commit-gnuradio] r5457 - gnuradio/branches/developers/matt/u2f/top/u2_b
From: |
matt |
Subject: |
[Commit-gnuradio] r5457 - gnuradio/branches/developers/matt/u2f/top/u2_basic |
Date: |
Thu, 10 May 2007 21:06:24 -0600 (MDT) |
Author: matt
Date: 2007-05-10 21:06:24 -0600 (Thu, 10 May 2007)
New Revision: 5457
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
working serdes loopback tester
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-11 03:05:17 UTC (rev 5456)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-05-11 03:06:24 UTC (rev 5457)
@@ -74,10 +74,10 @@
output ser_loopen,
output ser_rx_en,
- input ser_tx_clk,
- input [15:0] ser_t,
- input ser_tklsb,
- input ser_tkmsb,
+ output ser_tx_clk,
+ output [15:0] ser_t,
+ output ser_tklsb,
+ output ser_tkmsb,
input ser_rx_clk,
input [15:0] ser_r,
@@ -141,17 +141,9 @@
wire ram_loader_done;
wire ram_loader_rst, wb_rst, dsp_rst;
- wire [7:0] sysctrl_dbg;
- assign debug = {{dac_a},{dac_b}};
+ wire [31:0] ser_debug;
- // assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
- //
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
- // {sysctrl_dbg},
- // {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
- assign debug_clk[0] = wb_clk;
- assign debug_clk[1] = dsp_clk;
-
parameter dw = 32; // Data bus width
parameter aw = 16; // Address bus width, for byte addressibility, 16 =
64K byte memory space
parameter sw = 4; // Select width -- 32-bit data bus with 8-bit
granularity.
@@ -265,22 +257,22 @@
simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[0]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[7:0]),.dat_o(s3_dat_i[7:0]),.ack_o(s3_ack_a),
- .gpio(io_tx[7:0]) );
+ .gpio(/* io_tx[7:0]*/) );
simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[1]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[15:8]),.dat_o(s3_dat_i[15:8]),.ack_o(s3_ack_b),
- .gpio(io_tx[15:8]) );
+ .gpio(/* io_tx[15:8] */) );
simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[2]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[23:16]),.dat_o(s3_dat_i[23:16]),.ack_o(s3_ack_c),
- .gpio(io_rx[7:0]) );
+ .gpio(/* io_rx[7:0] */) );
simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[3]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[31:24]),.dat_o(s3_dat_i[31:24]),.ack_o(s3_ack_d),
- .gpio(io_rx[15:8]) );
+ .gpio(/* io_rx[15:8]*/) );
assign s3_err = 1'b0;
assign s3_rty = 1'b0;
@@ -330,11 +322,11 @@
.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
);
- assign s6_ack = 1'b0;
+ assign s6_ack = s6_stb;
assign s6_err = 1'b0;
assign s6_rty = 1'b0;
assign s6_dat_i = 32'd0;
- assign s7_ack = 1'b0;
+ assign s7_ack = s7_stb;
assign s7_err = 1'b0;
assign s7_rty = 1'b0;
assign s7_dat_i = 32'd0;
@@ -366,6 +358,39 @@
assign s5_err = 1'b0;
assign s5_rty = 1'b0;
+
+ assign dsp_rst = wb_rst;
+
+ // SERDES
+ serdes serdes
+ (.clk(dsp_clk),.rst(dsp_rst),
+
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+ .dout(),.rd_rdy(),.read(),
+ .din(ser_debug),.write(),.done(),.wr_rdy()
+ );
+
+
+
+ // Debug Pins
+ wire [31:0]
debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+ {8'hAF},
+ {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+
+ wire [31:0]
debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
+ {iram_rd_adr[15:8]},
+ {iram_rd_adr[7:0]},
+ {serdes_outs}};
+
+ assign io_rx = ser_debug[31:16];
+ assign io_tx = ser_debug[15:0];
+
+ assign debug = debug_wb;
+
+ assign debug_clk[0] = wb_clk;
+ assign debug_clk[1] = dsp_clk;
+
endmodule // u2_basic
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