[Commit-gnuradio] r5261 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-05-08 21:37:04 -0600 (Tue, 08 May 2007)
New Revision: 5261

Added:
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v
Log:
first cut at a skeleton dsp core


Added: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v                    
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core.v    2007-05-09 
03:37:04 UTC (rev 5261)
@@ -0,0 +1,79 @@
+
+module dsp_core 
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [15:0] wb_adr_i,
+   input [3:0] wb_sel_i,
+   input [31:0] wb_dat_i,
+   output [31:0] wb_dat_o,
+   output wb_ack_o,
+   
+   input dsp_clk,
+   input dsp_rst,
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b
+   );
+
+   assign       wb_dat_o = 32'd0;  // No readback for now
+
+   wire [15:0]          i, q, scale_i, scale_q;
+   wire [31:0]          phase_inc;
+   reg [31:0]   phase;
+   
+   wb_regfile_2clock
+     regs (.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
+          .wb_stb_i(wb_stb_i),.wb_we_i(wb_we_i),
+          .wb_adr_i(wb_adr_i),.wb_dat_i(wb_dat_i),
+          .wb_sel_i(wb_sel_i),.wb_ack_o(wb_ack_o),
+          .alt_clk(dsp_clk),.alt_rst(dsp_rst),
+          .reg00({i,q}),
+          .reg01(phase_inc),
+          .reg02({scale_i,scale_q}),
+          .reg03(),
+          .reg04(),
+          .reg05(),
+          .reg06(),
+          .reg07()
+          );
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   wire         signed [15:0]   da, db;
+   reg                  signed [15:0]   dar, dbr;
+   reg                  signed [35:0] prod_i, prod_q;
+   
+   cordic cordic(.clock(dsp_clk), 
+                .reset(dsp_rst),
+                .enable(1'b1),
+                .xi(i),.yi(q),.zi(phase[31:16]),
+                .xo(da),.yo(db),.zo() );
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       prod_i <= 36'sd0;
+     else
+       prod_i <= {{2{da[15]}},da} * {{2{scale_i[15]}},scale_i};
+
+   always @(posedge dsp_clk)
+     if(dsp_rst)
+       prod_q <= 36'sd0;
+     else
+       prod_q <= {{2{db[15]}},db} * {{2{scale_q[15]}},scale_q};
+
+   always @(posedge dsp_clk)
+     dac_a <= prod_i[23:8];
+
+   always @(posedge dsp_clk)
+     dac_b <= prod_q[23:8];
+   
+endmodule // dsp_core