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[Commit-gnuradio] r5258 - in gnuradio/branches/developers/matt/u2f/openc
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r5258 - in gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode: bench/verilog rtl/verilog rtl/verilog/CVS rtl/verilog/MAC_rx rtl/verilog/MAC_tx rtl/verilog/MAC_tx/CVS rtl/verilog/RMON rtl/verilog/TECH rtl/verilog/TECH/CVS rtl/verilog/miim |
|
Date: |
Tue, 8 May 2007 21:32:55 -0600 (MDT) |
Author: matt
Date: 2007-05-08 21:32:54 -0600 (Tue, 08 May 2007)
New Revision: 5258
Added:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v
Removed:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/Ramdon_gen.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_DIV2.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/host_sim.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/reg_int_sim.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/tb_top.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/Clk_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_clockgen.v
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v
Log:
changes to get this crap to compile
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -51,52 +51,52 @@
`timescale 1ns/100ps
-module Phy_sim (
-input Gtx_clk ,//used only in
GMII mode
-output Rx_clk ,
-output Tx_clk ,//used only in
MII mode
-input Tx_er ,
-input Tx_en ,
-input [7:0] Txd ,
-output Rx_er ,
-output Rx_dv ,
-output [7:0] Rxd ,
-output Crs ,
-output Col ,
-input [2:0] Speed
-);
-//////////////////////////////////////////////////////////////////////
-// this file used to simulate Phy.
-// generate clk and loop the Tx data to Rx data
-// full duplex mode can be verified on loop mode.
-//////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-// internal signals
-//////////////////////////////////////////////////////////////////////
-reg Clk_25m ;//used for 100 Mbps
mode
-reg Clk_2_5m ;//used for 10 Mbps mode
-//wire Rx_clk ;
-//wire Tx_clk ;//used only in MII mode
-//////////////////////////////////////////////////////////////////////
-always
- begin
+module Phy_sim (input Gtx_clk
,//used only in GMII mode
+ output Rx_clk
,
+ output Tx_clk
,//used only in MII mode
+ input Tx_er
,
+ input Tx_en
,
+ input [7:0] Txd
,
+ output Rx_er
,
+ output Rx_dv
,
+ output [7:0] Rxd
,
+ output Crs
,
+ output Col
,
+ input [2:0] Speed
+ );
+
+ // ////////////////////////////////////////////////////////////////////
+ // this file used to simulate Phy.
+ // generate clk and loop the Tx data to Rx data
+ // full duplex mode can be verified on loop mode.
+ // ////////////////////////////////////////////////////////////////////
+ // ////////////////////////////////////////////////////////////////////
+ // internal signals
+ // ////////////////////////////////////////////////////////////////////
+ reg Clk_25m ;//used for 100 Mbps
mode
+ reg Clk_2_5m ;//used for 10 Mbps mode
+ //wire Rx_clk ;
+ //wire Tx_clk ;//used only in MII mode
+ // ////////////////////////////////////////////////////////////////////
+ always
+ begin
#20 Clk_25m=0;
#20 Clk_25m=1;
- end
-
-always
- begin
+ end
+
+ always
+ begin
#200 Clk_2_5m=0;
#200 Clk_2_5m=1;
- end
-
-assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
-assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
-
-assign Rx_dv =Tx_en ;
-assign Rxd =Txd ;
-assign Rx_er =0 ;
-assign Crs =Tx_en ;
-assign Col =0 ;
-
-endmodule
\ No newline at end of file
+ end
+
+ assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
+ assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
+
+ assign Rx_dv =Tx_en ;
+ assign Rxd =Txd ;
+ assign Rx_er =0 ;
+ assign Crs =Tx_en ;
+ assign Col =0 ;
+
+endmodule // Phy_sim
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -51,101 +51,98 @@
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
-module User_int_sim (
-Reset ,
-Clk_user ,
-CPU_init_end ,
-//user inputerface ,
-Rx_mac_ra ,
-Rx_mac_rd ,
-Rx_mac_data ,
-Rx_mac_BE ,
-Rx_mac_pa ,
-Rx_mac_sop ,
-Rx_mac_eop ,
-//user inputerface ,
-Tx_mac_wa ,
-Tx_mac_wr ,
-Tx_mac_data ,
-Tx_mac_BE ,
-Tx_mac_sop ,
-Tx_mac_eop
-);
-input Reset ;
-input Clk_user ;
-input CPU_init_end ;
- //user inputerface
-input Rx_mac_ra ;
-output Rx_mac_rd ;
-input [31:0] Rx_mac_data ;
-input [1:0] Rx_mac_BE ;
-input Rx_mac_pa ;
-input Rx_mac_sop ;
-input Rx_mac_eop ;
- //user inputerface
-input Tx_mac_wa ;
-output Tx_mac_wr ;
-output [31:0] Tx_mac_data ;
-output [1:0] Tx_mac_BE ;//big endian
-output Tx_mac_sop ;
-output Tx_mac_eop ;
+module User_int_sim (Reset ,
+ Clk_user ,
+ CPU_init_end ,
+ //user inputerface ,
+ Rx_mac_ra ,
+ Rx_mac_rd ,
+ Rx_mac_data ,
+ Rx_mac_BE ,
+ Rx_mac_pa ,
+ Rx_mac_sop ,
+ Rx_mac_eop ,
+ //user inputerface ,
+ Tx_mac_wa ,
+ Tx_mac_wr ,
+ Tx_mac_data ,
+ Tx_mac_BE ,
+ Tx_mac_sop ,
+ Tx_mac_eop
+ );
-//////////////////////////////////////////////////////////////////////
-// inputernal signals
-//////////////////////////////////////////////////////////////////////
-reg[4:0] operation;
-reg[31:0] data;
-reg Rx_mac_rd;
-reg Start_tran;
-//////////////////////////////////////////////////////////////////////
-//generate Tx user data
-//////////////////////////////////////////////////////////////////////
-initial
- begin
+ input Reset ;
+ input Clk_user ;
+ input CPU_init_end ;
+ //user inputerface
+ input Rx_mac_ra ;
+ output Rx_mac_rd ;
+ input [31:0] Rx_mac_data ;
+ input [1:0] Rx_mac_BE
;
+ input Rx_mac_pa ;
+ input Rx_mac_sop ;
+ input Rx_mac_eop ;
+ //user inputerface
+ input Tx_mac_wa ;
+ output Tx_mac_wr ;
+ output [31:0] Tx_mac_data ;
+ output [1:0] Tx_mac_BE ;//big
endian
+ output Tx_mac_sop ;
+ output Tx_mac_eop ;
+
+ // ////////////////////////////////////////////////////////////////////
+ // inputernal signals
+ // ////////////////////////////////////////////////////////////////////
+ reg [4:0] operation;
+ reg [31:0] data;
+ reg Rx_mac_rd;
+ reg Start_tran;
+ // ////////////////////////////////////////////////////////////////////
+ //generate Tx user data
+ // ////////////////////////////////////////////////////////////////////
+ initial
+ begin
operation =0;
data =0;
- end
-
-always @ (posedge Clk_user or posedge Reset)
- if (Reset)
- Start_tran <=0;
- else if (Tx_mac_eop&&!Tx_mac_wa)
- Start_tran <=0;
- else if (Tx_mac_wa)
- Start_tran <=1;
-
-
-always @ (posedge Clk_user)
- if (Tx_mac_wa&&CPU_init_end)
- $ip_32W_gen("../data/config.ini",operation,data);
- else
- begin
- operation <=0;
- data <=0;
- end
-
-assign Tx_mac_data =data;
-assign Tx_mac_wr =operation[4];
-assign Tx_mac_sop =operation[3];
-assign Tx_mac_eop =operation[2];
-assign Tx_mac_BE =operation[1:0];
-//////////////////////////////////////////////////////////////////////
-//verify Rx user data
-//////////////////////////////////////////////////////////////////////
-always @ (posedge Clk_user or posedge Reset)
- if (Reset)
- Rx_mac_rd <=0;
- else if(Rx_mac_ra)
- Rx_mac_rd <=1;
- else
- Rx_mac_rd <=0;
-
-
-always @ (posedge Clk_user )
- if (Rx_mac_pa)
- $ip_32W_check( Rx_mac_data,
-
{Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
-
-endmodule
-
\ No newline at end of file
+ end
+
+ always @ (posedge Clk_user or posedge Reset)
+ if (Reset)
+ Start_tran <=0;
+ else if (Tx_mac_eop&&!Tx_mac_wa)
+ Start_tran <=0;
+ else if (Tx_mac_wa)
+ Start_tran <=1;
+
+ always @ (posedge Clk_user)
+ if (Tx_mac_wa&&CPU_init_end)
+ $ip_32W_gen("../data/config.ini",operation,data);
+ else
+ begin
+ operation <=0;
+ data <=0;
+ end
+
+ assign Tx_mac_data =data;
+ assign Tx_mac_wr =operation[4];
+ assign Tx_mac_sop =operation[3];
+ assign Tx_mac_eop =operation[2];
+ assign Tx_mac_BE =operation[1:0];
+ //////////////////////////////////////////////////////////////////////
+ //verify Rx user data
+ //////////////////////////////////////////////////////////////////////
+ always @ (posedge Clk_user or posedge Reset)
+ if (Reset)
+ Rx_mac_rd <=0;
+ else if(Rx_mac_ra)
+ Rx_mac_rd <=1;
+ else
+ Rx_mac_rd <=0;
+
+ always @ (posedge Clk_user )
+ if (Rx_mac_pa)
+ $ip_32W_check( Rx_mac_data,
+ {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
+
+endmodule // User_int_sim
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/host_sim.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/host_sim.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/host_sim.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,83 +1,77 @@
-module host_sim (
-input Reset ,
-input Clk_reg ,
-output reg CSB ,
-output reg WRB ,
-output reg CPU_init_end ,
-output reg [15:0] CD_in ,
-input [15:0] CD_out ,
-output reg [7:0] CA
-);
-////////////////////////////////////////
-task CPU_init;
-begin
- CA =0;
- CD_in =0;
- WRB =1;
- CSB =1;
-end
-endtask
+module host_sim
+ (input Reset
,
+ input Clk_reg
,
+ output reg CSB ,
+ output reg WRB ,
+ output reg CPU_init_end ,
+ output reg [15:0] CD_in ,
+ input [15:0] CD_out ,
+ output reg [7:0] CA
+ );
-////////////////////////////////////////
-task CPU_wr;
-input[6:0] Addr;
-input[15:0] Data;
-begin
- CA ={Addr,1'b0};
- CD_in =Data;
- WRB =0;
- CSB =0;
-#20;
- CA =0;
- CD_in =0;
- WRB =1;
- CSB =1;
-#20;
-end
-endtask
-/////////////////////////////////////////
-task CPU_rd;
-input[6:0] Addr;
-begin
- CA ={Addr,1'b0};
- WRB =1;
- CSB =0;
-#20;
- CA =0;
- WRB =1;
- CSB =1;
-#20;
-end
-endtask
-/////////////////////////////////////////
+ ////////////////////////////////////////
+ task CPU_init;
+ begin
+ CA =0;
+ CD_in =0;
+ WRB =1;
+ CSB =1;
+ end
+ endtask
-integer i;
-
-reg [31:0] CPU_data [255:0];
-reg [7:0] write_times;
-reg [7:0] write_add;
-reg [15:0] write_data;
-
-
-initial
- begin
-
- end
-
-
-initial
- begin
+ ////////////////////////////////////////
+ task CPU_wr;
+ input[6:0] Addr;
+ input[15:0] Data;
+ begin
+ CA ={Addr,1'b0};
+ CD_in =Data;
+ WRB =0;
+ CSB =0;
+ #20;
+ CA =0;
+ CD_in =0;
+ WRB =1;
+ CSB =1;
+ #20;
+ end
+ endtask
+ /////////////////////////////////////////
+ task CPU_rd;
+ input[6:0] Addr;
+ begin
+ CA ={Addr,1'b0};
+ WRB =1;
+ CSB =0;
+ #20;
+ CA =0;
+ WRB =1;
+ CSB =1;
+ #20;
+ end
+ endtask
+ /////////////////////////////////////////
+
+ integer i;
+
+ reg [31:0] CPU_data [255:0];
+ reg [7:0] write_times;
+ reg [7:0] write_add;
+ reg [15:0] write_data;
+
+ initial
+ begin
CPU_init;
CPU_init_end=0;
$readmemh("../data/CPU.vec",CPU_data);
{write_times,write_add,write_data}=CPU_data[0];
- #90 ;
+ #90 ;
for (i=0;i<write_times;i=i+1)
- begin
- {write_times,write_add,write_data}=CPU_data[i];
- CPU_wr(write_add[6:0],write_data);
- end
+ begin
+ {write_times,write_add,write_data}=CPU_data[i];
+ CPU_wr(write_add[6:0],write_data);
+ end
CPU_init_end=1;
- end
-endmodule
\ No newline at end of file
+ end
+endmodule // host_sim
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/reg_int_sim.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/reg_int_sim.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/reg_int_sim.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -99,37 +99,37 @@
input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA
register with read data
);
-assign Tx_Hwmark =5'h1e;
-assign Tx_Lwmark =5'h19;
-assign pause_frame_send_en =0;
-assign pause_quanta_set =0;
-assign MAC_tx_add_en =0;
-assign FullDuplex =1;
-assign MaxRetry =2;
-assign IFGset =10;
-assign MAC_tx_add_prom_data =0;
-assign MAC_tx_add_prom_add =0;
-assign MAC_tx_add_prom_wr =0;
-assign tx_pause_en =0;
-assign xoff_cpu =0;
-assign xon_cpu =0;
-
-assign MAC_rx_add_chk_en =0;
-assign MAC_rx_add_prom_data =0;
-assign MAC_rx_add_prom_add =0;
-assign MAC_rx_add_prom_wr =0;
-assign broadcast_filter_en =0;
-assign broadcast_MAX =10;
-assign RX_APPEND_CRC =0;
-assign CRC_chk_en =1;
-assign RX_IFG_SET =10;
-assign RX_MAX_LENGTH =1518;
-assign RX_MIN_LENGTH =64;
-
-assign CPU_rd_addr =0;
-assign CPU_rd_apply =0;
-
-assign Line_loop_en =0;
-assign Speed =3'b001;
-
-endmodule
\ No newline at end of file
+ assign Tx_Hwmark =5'h1e;
+ assign Tx_Lwmark =5'h19;
+ assign pause_frame_send_en =0;
+ assign pause_quanta_set =0;
+ assign MAC_tx_add_en =0;
+ assign FullDuplex =1;
+ assign MaxRetry =2;
+ assign IFGset =10;
+ assign MAC_tx_add_prom_data =0;
+ assign MAC_tx_add_prom_add =0;
+ assign MAC_tx_add_prom_wr =0;
+ assign tx_pause_en =0;
+ assign xoff_cpu =0;
+ assign xon_cpu =0;
+
+ assign MAC_rx_add_chk_en =0;
+ assign MAC_rx_add_prom_data =0;
+ assign MAC_rx_add_prom_add =0;
+ assign MAC_rx_add_prom_wr =0;
+ assign broadcast_filter_en =0;
+ assign broadcast_MAX =10;
+ assign RX_APPEND_CRC =0;
+ assign CRC_chk_en =1;
+ assign RX_IFG_SET =10;
+ assign RX_MAX_LENGTH =1518;
+ assign RX_MIN_LENGTH =64;
+
+ assign CPU_rd_addr =0;
+ assign CPU_rd_apply =0;
+
+ assign Line_loop_en =0;
+ assign Speed =3'b001;
+
+endmodule // reg_int_sim
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/tb_top.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/tb_top.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/verilog/tb_top.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -51,182 +51,180 @@
// no message
//
-module tb_top (
-);
-//******************************************************************************
-//internal signals
-//******************************************************************************
- //system signals
-reg Reset ;
-reg Clk_125M ;
-reg Clk_user ;
-reg Clk_reg ;
- //user interface
-wire Rx_mac_ra ;
-wire Rx_mac_rd ;
-wire [31:0] Rx_mac_data ;
-wire [1:0] Rx_mac_BE ;
-wire Rx_mac_pa ;
-wire Rx_mac_sop ;
-wire Rx_mac_eop ;
- //user interface
-wire Tx_mac_wa ;
-wire Tx_mac_wr ;
-wire [31:0] Tx_mac_data ;
-wire [1:0] Tx_mac_BE ;//big endian
-wire Tx_mac_sop ;
-wire Tx_mac_eop ;
- //Phy interface
- //Phy interface
-wire Gtx_clk ;//used only in
GMII mode
-wire Rx_clk ;
-wire Tx_clk ;//used only in
MII mode
-wire Tx_er ;
-wire Tx_en ;
-wire [7:0] Txd ;
-wire Rx_er ;
-wire Rx_dv ;
-wire [7:0] Rxd ;
-wire Crs ;
-wire Col ;
-wire CSB ;
-wire WRB ;
-wire [15:0] CD_in ;
-wire [15:0] CD_out ;
-wire [7:0] CA ;
- //Phy int host interface
-wire Line_loop_en ;
-wire [2:0] Speed ;
- //mii
-wire Mdio ;// MII Management Data In
-wire Mdc ;// MII Management Data Clock
-wire CPU_init_end ;
-//******************************************************************************
-//internal signals
-//******************************************************************************
+module tb_top ();
+ //
******************************************************************************
+ //internal signals
+ //
******************************************************************************
+ //system signals
-initial
- begin
- Reset =1;
+ reg Reset ;
+ reg Clk_125M ;
+ reg Clk_user ;
+ reg Clk_reg ;
+ //user interface
+ wire Rx_mac_ra ;
+ wire Rx_mac_rd ;
+ wire [31:0] Rx_mac_data
;
+ wire [1:0] Rx_mac_BE ;
+ wire Rx_mac_pa ;
+ wire Rx_mac_sop ;
+ wire Rx_mac_eop ;
+ //user interface
+ wire Tx_mac_wa ;
+ wire Tx_mac_wr ;
+ wire [31:0] Tx_mac_data ;
+ wire [1:0] Tx_mac_BE ;//big
endian
+ wire Tx_mac_sop ;
+ wire Tx_mac_eop ;
+ //Phy interface
+ //Phy interface
+ wire Gtx_clk ;//used
only in GMII mode
+ wire Rx_clk ;
+ wire Tx_clk ;//used
only in MII mode
+ wire Tx_er ;
+ wire Tx_en ;
+ wire [7:0] Txd
;
+ wire Rx_er ;
+ wire Rx_dv ;
+ wire [7:0] Rxd
;
+ wire Crs
;
+ wire Col
;
+ wire CSB ;
+ wire WRB ;
+ wire [15:0] CD_in ;
+ wire [15:0] CD_out ;
+ wire [7:0] CA ;
+ //Phy int host interface
+ wire Line_loop_en ;
+ wire [2:0] Speed ;
+ //mii
+ wire Mdio ;// MII Management Data
In
+ wire Mdc ;// MII
Management Data Clock
+ wire CPU_init_end ;
+ //
******************************************************************************
+ //internal signals
+ //
******************************************************************************
+
+ initial
+ begin
+ Reset =1;
#20 Reset =0;
- end
-always
- begin
+ end
+ always
+ begin
#4 Clk_125M=0;
#4 Clk_125M=1;
- end
-
-always
- begin
+ end
+
+ always
+ begin
#5 Clk_user=0;
#5 Clk_user=1;
- end
-
-always
- begin
+ end
+
+ always
+ begin
#10 Clk_reg=0;
#10 Clk_reg=1;
- end
+ end
+
+// initial
+ // begin
+ //$shm_open("tb_top.shm",,900000000,);
+// $shm_probe("AS");
+ // end
+ MAC_top
+ U_MAC_top(//system signals (//system signals
),
+ .Reset (Reset
),
+ .Clk_125M (Clk_125M
),
+ .Clk_user (Clk_user
),
+ .Clk_reg (Clk_reg
),
+ .Speed (Speed ),
+ //user interface (//user interface ),
+ .Rx_mac_ra (Rx_mac_ra
),
+ .Rx_mac_rd (Rx_mac_rd
),
+ .Rx_mac_data (Rx_mac_data
),
+ .Rx_mac_BE (Rx_mac_BE
),
+ .Rx_mac_pa (Rx_mac_pa
),
+ .Rx_mac_sop (Rx_mac_sop
),
+ .Rx_mac_eop (Rx_mac_eop
),
+ //user interface (//user interface ),
+ .Tx_mac_wa (Tx_mac_wa
),
+ .Tx_mac_wr (Tx_mac_wr
),
+ .Tx_mac_data (Tx_mac_data
),
+ .Tx_mac_BE (Tx_mac_BE
),
+ .Tx_mac_sop (Tx_mac_sop
),
+ .Tx_mac_eop (Tx_mac_eop
),
+ //Phy interface (//Phy interface ),
+ //Phy interface (//Phy interface
),
+ .Gtx_clk (Gtx_clk
),
+ .Rx_clk (Rx_clk
),
+ .Tx_clk (Tx_clk
),
+ .Tx_er (Tx_er
),
+ .Tx_en (Tx_en
),
+ .Txd (Txd
),
+ .Rx_er (Rx_er
),
+ .Rx_dv (Rx_dv
),
+ .Rxd (Rxd
),
+ .Crs (Crs
),
+ .Col (Col
),
+ //host interface
+ .CSB (CSB ),
+ .WRB (WRB ),
+ .CD_in (CD_in ),
+ .CD_out (CD_out ),
+ .CA (CA ),
+ //MII interface signals (//MII interface signals ),
+ .Mdio (Mdio ),
+ .Mdc (Mdc
)
+ );
+
+ Phy_sim
+ U_Phy_sim (.Gtx_clk
(Gtx_clk ),
+ .Rx_clk (Rx_clk
),
+ .Tx_clk (Tx_clk
),
+ .Tx_er (Tx_er
),
+ .Tx_en (Tx_en
),
+ .Txd (Txd
),
+ .Rx_er (Rx_er
),
+ .Rx_dv (Rx_dv
),
+ .Rxd (Rxd
),
+ .Crs (Crs
),
+ .Col (Col
),
+ .Speed (Speed
)
+ );
+
+ User_int_sim
+ U_User_int_sim(.Reset
(Reset ),
+ .Clk_user (Clk_user
),
+ .CPU_init_end (CPU_init_end
),
+ //user inputerface (//user inputerface
),
+ .Rx_mac_ra (Rx_mac_ra
),
+ .Rx_mac_rd (Rx_mac_rd
),
+ .Rx_mac_data (Rx_mac_data
),
+ .Rx_mac_BE (Rx_mac_BE
),
+ .Rx_mac_pa (Rx_mac_pa
),
+ .Rx_mac_sop (Rx_mac_sop
),
+ .Rx_mac_eop (Rx_mac_eop
),
+ //user inputerface (//user inputerface
),
+ .Tx_mac_wa (Tx_mac_wa
),
+ .Tx_mac_wr (Tx_mac_wr
),
+ .Tx_mac_data (Tx_mac_data
),
+ .Tx_mac_BE (Tx_mac_BE
),
+ .Tx_mac_sop (Tx_mac_sop
),
+ .Tx_mac_eop (Tx_mac_eop
)
+ );
+
+ host_sim
+ U_host_sim(.Reset (Reset
),
+ .Clk_reg (Clk_reg
),
+ .CSB (CSB ),
+ .WRB (WRB ),
+ .CD_in (CD_in ),
+ .CD_out (CD_out ),
+ .CPU_init_end (CPU_init_end ),
+ .CA (CA )
+ );
-initial
- begin
- $shm_open("tb_top.shm",,900000000,);
- $shm_probe("AS");
- end
-
-
-MAC_top U_MAC_top(
- //system signals (//system signals ),
-.Reset (Reset
),
-.Clk_125M (Clk_125M
),
-.Clk_user (Clk_user
),
-.Clk_reg (Clk_reg
),
-.Speed (Speed ),
- //user interface (//user interface ),
-.Rx_mac_ra (Rx_mac_ra
),
-.Rx_mac_rd (Rx_mac_rd
),
-.Rx_mac_data (Rx_mac_data
),
-.Rx_mac_BE (Rx_mac_BE
),
-.Rx_mac_pa (Rx_mac_pa
),
-.Rx_mac_sop (Rx_mac_sop
),
-.Rx_mac_eop (Rx_mac_eop
),
- //user interface (//user interface ),
-.Tx_mac_wa (Tx_mac_wa ),
-.Tx_mac_wr (Tx_mac_wr ),
-.Tx_mac_data (Tx_mac_data ),
-.Tx_mac_BE (Tx_mac_BE
),
-.Tx_mac_sop (Tx_mac_sop ),
-.Tx_mac_eop (Tx_mac_eop
),
- //Phy interface (//Phy interface ),
- //Phy interface (//Phy interface
),
-.Gtx_clk (Gtx_clk
),
-.Rx_clk (Rx_clk
),
-.Tx_clk (Tx_clk
),
-.Tx_er (Tx_er
),
-.Tx_en (Tx_en
),
-.Txd (Txd
),
-.Rx_er (Rx_er
),
-.Rx_dv (Rx_dv
),
-.Rxd (Rxd
),
-.Crs (Crs
),
-.Col (Col
),
-//host interface
-.CSB (CSB ),
-.WRB (WRB ),
-.CD_in (CD_in ),
-.CD_out (CD_out ),
-.CA (CA ),
- //MII interface signals (//MII interface signals ),
-.Mdio (Mdio ),
-.Mdc (Mdc )
-);
-
-Phy_sim U_Phy_sim (
-.Gtx_clk (Gtx_clk
),
-.Rx_clk (Rx_clk
),
-.Tx_clk (Tx_clk
),
-.Tx_er (Tx_er ),
-.Tx_en (Tx_en ),
-.Txd (Txd ),
-.Rx_er (Rx_er ),
-.Rx_dv (Rx_dv ),
-.Rxd (Rxd ),
-.Crs (Crs ),
-.Col (Col ),
-.Speed (Speed )
-);
-
-User_int_sim U_User_int_sim(
-.Reset (Reset
),
-.Clk_user (Clk_user
),
-.CPU_init_end (CPU_init_end ),
- //user inputerface (//user inputerface ),
-.Rx_mac_ra (Rx_mac_ra
),
-.Rx_mac_rd (Rx_mac_rd
),
-.Rx_mac_data (Rx_mac_data ),
-.Rx_mac_BE (Rx_mac_BE
),
-.Rx_mac_pa (Rx_mac_pa
),
-.Rx_mac_sop (Rx_mac_sop
),
-.Rx_mac_eop (Rx_mac_eop
),
- //user inputerface (//user inputerface ),
-.Tx_mac_wa (Tx_mac_wa ),
-.Tx_mac_wr (Tx_mac_wr ),
-.Tx_mac_data (Tx_mac_data ),
-.Tx_mac_BE (Tx_mac_BE
),
-.Tx_mac_sop (Tx_mac_sop ),
-.Tx_mac_eop (Tx_mac_eop
)
-);
-
-host_sim U_host_sim(
-.Reset (Reset ),
-.Clk_reg (Clk_reg ),
-.CSB (CSB ),
-.WRB (WRB ),
-.CD_in (CD_in ),
-.CD_out (CD_out ),
-.CPU_init_end (CPU_init_end ),
-.CA (CA )
-
-);
-endmodule
+endmodule // tb_top
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,14 +1,14 @@
/Clk_ctrl.v/1.3/Thu Jan 19 14:07:52 2006//
/MAC_rx.v/1.4/Fri Nov 17 17:53:07 2006//
-/MAC_top.v/1.3/Thu Jan 19 14:07:52 2006//
/MAC_tx.v/1.4/Fri Nov 17 17:53:07 2006//
/Phy_int.v/1.3/Thu Jan 19 14:07:53 2006//
/RMON.v/1.4/Sun Jun 25 04:58:56 2006//
/eth_miim.v/1.3/Thu Jan 19 14:07:53 2006//
-/header.v/1.1/Thu Jan 19 14:07:53 2006//
/reg_int.v/1.4/Fri Nov 17 17:53:07 2006//
D/MAC_rx////
D/MAC_tx////
D/RMON////
D/TECH////
D/miim////
+/MAC_top.v/1.3/Tue May 1 07:30:08 2007//
+/header.v/1.1/Tue May 1 07:35:45 2007//
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/Clk_ctrl.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/Clk_ctrl.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/Clk_ctrl.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -91,13 +91,13 @@
assign Gtx_clk =Clk_125M ;
assign MAC_rx_clk =Rx_clk ;
-CLK_DIV2 U_0_CLK_DIV2(
+clkdiv2 U_0_CLK_DIV2(
.Reset (Reset ),
.IN (Rx_clk ),
.OUT (Rx_clk_div2 )
);
-CLK_DIV2 U_1_CLK_DIV2(
+clkdiv2 U_1_CLK_DIV2(
.Reset (Reset ),
.IN (Tx_clk ),
.OUT (Tx_clk_div2 )
@@ -124,4 +124,4 @@
.SW (Speed[2] ),
.OUT (MAC_tx_clk_div )
);
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -59,659 +59,601 @@
// no message
//
-module MAC_rx_FF (
-Reset ,
-Clk_MAC ,
-Clk_SYS ,
-//MAC_rx_ctrl interface
-Fifo_data ,
-Fifo_data_en ,
-Fifo_full ,
-Fifo_data_err ,
-Fifo_data_end ,
-//CPU
-Rx_Hwmark,
-Rx_Lwmark,
-RX_APPEND_CRC,
-//user interface
-Rx_mac_ra ,
-Rx_mac_rd ,
-Rx_mac_data ,
-Rx_mac_BE ,
-Rx_mac_sop ,
-Rx_mac_pa,
-Rx_mac_eop
-);
-input Reset ;
-input Clk_MAC ;
-input Clk_SYS ;
- //MAC_rx_ctrl interface
-input [7:0] Fifo_data ;
-input Fifo_data_en ;
-output Fifo_full ;
-input Fifo_data_err ;
-input Fifo_data_end ;
- //CPU
-input RX_APPEND_CRC ;
-input [4:0] Rx_Hwmark ;
-input [4:0] Rx_Lwmark ;
- //user interface
-output Rx_mac_ra ;//
-input Rx_mac_rd ;
-output [31:0] Rx_mac_data ;
-output [1:0] Rx_mac_BE ;
-output Rx_mac_pa ;
-output Rx_mac_sop ;
-output Rx_mac_eop ;
+module MAC_rx_FF
+ #(parameter MAC_RX_FF_DEPTH = 9)
+ (Reset,Clk_MAC,Clk_SYS,
+ //MAC_rx_ctrl interface
+ Fifo_data,Fifo_data_en,Fifo_full,Fifo_data_err,Fifo_data_end,
+ //CPU
+ Rx_Hwmark,Rx_Lwmark,RX_APPEND_CRC,
+ //user interface
+
Rx_mac_ra,Rx_mac_rd,Rx_mac_data,Rx_mac_BE,Rx_mac_sop,Rx_mac_pa,Rx_mac_eop);
-//******************************************************************************
-//internal signals
-//******************************************************************************
-parameter State_byte3 =4'd0;
-parameter State_byte2 =4'd1;
-parameter State_byte1 =4'd2;
-parameter State_byte0 =4'd3;
-parameter State_be0 =4'd4;
-parameter State_be3 =4'd5;
-parameter State_be2 =4'd6;
-parameter State_be1 =4'd7;
-parameter State_err_end =4'd8;
-parameter State_idle =4'd9;
+ input Reset;
+ input Clk_MAC ;
+ input Clk_SYS ;
+ //MAC_rx_ctrl interface
+ input [7:0] Fifo_data ;
+ input Fifo_data_en ;
+ output Fifo_full ;
+ input Fifo_data_err ;
+ input Fifo_data_end ;
+ //CPU
+ input RX_APPEND_CRC ;
+ input [4:0] Rx_Hwmark ;
+ input [4:0] Rx_Lwmark ;
+ //user interface
+ output Rx_mac_ra ;//
+ input Rx_mac_rd ;
+ output [31:0] Rx_mac_data ;
+ output [1:0] Rx_mac_BE ;
+ output Rx_mac_pa ;
+ output Rx_mac_sop ;
+ output Rx_mac_eop ;
+
+ //
******************************************************************************
+ //internal signals
+ //
******************************************************************************
+ parameter State_byte3 =4'd0;
+ parameter State_byte2 =4'd1;
+ parameter State_byte1 =4'd2;
+ parameter State_byte0 =4'd3;
+ parameter State_be0 =4'd4;
+ parameter State_be3 =4'd5;
+ parameter State_be2 =4'd6;
+ parameter State_be1 =4'd7;
+ parameter State_err_end =4'd8;
+ parameter State_idle =4'd9;
+
+ parameter SYS_read =3'd0;
+ parameter SYS_pause =3'd1;
+ parameter SYS_wait_end =3'd2;
+ parameter SYS_idle =3'd3;
+ parameter FF_emtpy_err =3'd4;
+
+ reg [MAC_RX_FF_DEPTH-1:0] Add_wr;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
+
+ reg [MAC_RX_FF_DEPTH-1:0] Add_rd;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
+ reg [MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
+ reg [35:0] Din;
+ reg [35:0] Din_tmp;
+ reg [35:0] Din_tmp_reg;
+ wire [35:0] Dout;
+ reg Wr_en;
+ reg Wr_en_tmp;
+ reg Wr_en_ptr;
+ wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
+ wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
+ wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
+ wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
+ reg Full;
+ reg Almost_full;
+ reg Empty /* synthesis syn_keep=1 */;
+ reg [3:0] Current_state /* synthesis syn_keep=1 */;
+ reg [3:0] Next_state;
+ reg [7:0] Fifo_data_byte0;
+ reg [7:0] Fifo_data_byte1;
+ reg [7:0] Fifo_data_byte2;
+ reg [7:0] Fifo_data_byte3;
+ reg Fifo_data_en_dl1;
+ reg [7:0] Fifo_data_dl1;
+ reg Rx_mac_sop_tmp ;
+ reg Rx_mac_sop ;
+ reg Rx_mac_ra ;
+ reg Rx_mac_pa ;
+
+
+
+ reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
+ reg [2:0] Next_state_SYS ;
+ reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
+ reg Packet_number_sub ;
+ wire Packet_number_add_edge;
+ reg Packet_number_add_dl1;
+ reg Packet_number_add_dl2;
+ reg Packet_number_add ;
+ reg Packet_number_add_tmp ;
+ reg Packet_number_add_tmp_dl1;
+ reg Packet_number_add_tmp_dl2;
+
+ reg Rx_mac_sop_tmp_dl1;
+ reg [35:0] Dout_dl1;
+ reg [4:0] Fifo_data_count;
+ reg Rx_mac_pa_tmp ;
+ reg Add_wr_jump_tmp ;
+ reg Add_wr_jump_tmp_pl1 ;
+ reg Add_wr_jump ;
+ reg Add_wr_jump_rd_pl1 ;
+ reg [4:0] Rx_Hwmark_pl ;
+ reg [4:0] Rx_Lwmark_pl ;
+ integer i ;
+
+ //
******************************************************************************
+ //domain Clk_MAC,write data to dprom.a-port for write
+ //
******************************************************************************
-parameter SYS_read =3'd0;
-parameter SYS_pause =3'd1;
-parameter SYS_wait_end =3'd2;
-parameter SYS_idle =3'd3;
-parameter FF_emtpy_err =3'd4;
-
-reg [`MAC_TX_FF_DEPTH-1:0] Add_wr;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_ungray;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_reg;
-
-reg [`MAC_TX_FF_DEPTH-1:0] Add_rd;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1;
-reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_ungray;
-reg [35:0] Din;
-reg [35:0] Din_tmp;
-reg [35:0] Din_tmp_reg;
-wire[35:0] Dout;
-reg Wr_en;
-reg Wr_en_tmp;
-reg Wr_en_ptr;
-wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse;
-wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse4;
-wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse3;
-wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse2;
-reg Full;
-reg Almost_full;
-reg Empty /* synthesis syn_keep=1 */;
-reg [3:0] Current_state /* synthesis syn_keep=1 */;
-reg [3:0] Next_state;
-reg [7:0] Fifo_data_byte0;
-reg [7:0] Fifo_data_byte1;
-reg [7:0] Fifo_data_byte2;
-reg [7:0] Fifo_data_byte3;
-reg Fifo_data_en_dl1;
-reg [7:0] Fifo_data_dl1;
-reg Rx_mac_sop_tmp ;
-reg Rx_mac_sop ;
-reg Rx_mac_ra ;
-reg Rx_mac_pa ;
-
-
-
-reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
-reg [2:0] Next_state_SYS ;
-reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
-reg Packet_number_sub ;
-wire Packet_number_add_edge;
-reg Packet_number_add_dl1;
-reg Packet_number_add_dl2;
-reg Packet_number_add ;
-reg Packet_number_add_tmp ;
-reg Packet_number_add_tmp_dl1;
-reg Packet_number_add_tmp_dl2;
-
-reg Rx_mac_sop_tmp_dl1;
-reg [35:0] Dout_dl1;
-reg [4:0] Fifo_data_count;
-reg Rx_mac_pa_tmp ;
-reg Add_wr_jump_tmp ;
-reg Add_wr_jump_tmp_pl1 ;
-reg Add_wr_jump ;
-reg Add_wr_jump_rd_pl1 ;
-reg [4:0] Rx_Hwmark_pl ;
-reg [4:0] Rx_Lwmark_pl ;
-integer i ;
-//******************************************************************************
-//domain Clk_MAC,write data to dprom.a-port for write
-//******************************************************************************
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Current_state <=State_idle;
- else
- Current_state <=Next_state;
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Current_state <=State_idle;
+ else
+ Current_state <=Next_state;
+
+ always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
+ case (Current_state)
+ State_idle:
+ if (Fifo_data_en)
+ Next_state =State_byte3;
+ else
+ Next_state =Current_state;
+ State_byte3:
+ if (Fifo_data_en)
+ Next_state =State_byte2;
+ else if (Fifo_data_err)
+ Next_state =State_err_end;
+ else if (Fifo_data_end)
+ Next_state =State_be1;
+ else
+ Next_state =Current_state;
+ State_byte2:
+ if (Fifo_data_en)
+ Next_state =State_byte1;
+ else if (Fifo_data_err)
+ Next_state =State_err_end;
+ else if (Fifo_data_end)
+ Next_state =State_be2;
+ else
+ Next_state =Current_state;
+ State_byte1:
+ if (Fifo_data_en)
+ Next_state =State_byte0;
+ else if (Fifo_data_err)
+ Next_state =State_err_end;
+ else if (Fifo_data_end)
+ Next_state =State_be3;
+ else
+ Next_state =Current_state;
+ State_byte0:
+ if (Fifo_data_en)
+ Next_state =State_byte3;
+ else if (Fifo_data_err)
+ Next_state =State_err_end;
+ else if (Fifo_data_end)
+ Next_state =State_be0;
+ else
+ Next_state =Current_state;
+ State_be1:
+ Next_state =State_idle;
+ State_be2:
+ Next_state =State_idle;
+ State_be3:
+ Next_state =State_idle;
+ State_be0:
+ Next_state =State_idle;
+ State_err_end:
+ Next_state =State_idle;
+ default:
+ Next_state =State_idle;
+ endcase
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_reg <=0;
+ else if (Current_state==State_idle)
+ Add_wr_reg <=Add_wr;
-always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
- case (Current_state)
- State_idle:
- if (Fifo_data_en)
- Next_state =State_byte3;
- else
- Next_state =Current_state;
- State_byte3:
- if (Fifo_data_en)
- Next_state =State_byte2;
- else if (Fifo_data_err)
- Next_state =State_err_end;
- else if (Fifo_data_end)
- Next_state =State_be1;
- else
- Next_state =Current_state;
- State_byte2:
- if (Fifo_data_en)
- Next_state =State_byte1;
- else if (Fifo_data_err)
- Next_state =State_err_end;
- else if (Fifo_data_end)
- Next_state =State_be2;
- else
- Next_state =Current_state;
- State_byte1:
- if (Fifo_data_en)
- Next_state =State_byte0;
- else if (Fifo_data_err)
- Next_state =State_err_end;
- else if (Fifo_data_end)
- Next_state =State_be3;
- else
- Next_state =Current_state;
- State_byte0:
- if (Fifo_data_en)
- Next_state =State_byte3;
- else if (Fifo_data_err)
- Next_state =State_err_end;
- else if (Fifo_data_end)
- Next_state =State_be0;
- else
- Next_state =Current_state;
- State_be1:
- Next_state =State_idle;
- State_be2:
- Next_state =State_idle;
- State_be3:
- Next_state =State_idle;
- State_be0:
- Next_state =State_idle;
- State_err_end:
- Next_state =State_idle;
- default:
- Next_state =State_idle;
- endcase
-
-//
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_reg <=0;
- else if (Current_state==State_idle)
- Add_wr_reg <=Add_wr;
-
-//
-
-
-always @ (posedge Reset or posedge Clk_MAC)
- if (Reset)
- Add_wr_gray <=0;
- else
- begin
- Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
- end
-
-//
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_gray_dl1 <=0;
- else
- Add_rd_gray_dl1 <=Add_rd_gray;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_ungray =0;
- else
- begin
- Add_rd_ungray[`MAC_RX_FF_DEPTH-1]
=Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_rd_ungray[i]
=Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
- end
-assign Add_wr_pluse=Add_wr+1;
-assign Add_wr_pluse4=Add_wr+4;
-assign Add_wr_pluse3=Add_wr+3;
-assign Add_wr_pluse2=Add_wr+2;
-
-
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Full <=0;
- else if (Add_wr_pluse==Add_rd_ungray)
- Full <=1;
- else
- Full <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Almost_full <=0;
- else if (Add_wr_pluse4==Add_rd_ungray||
- Add_wr_pluse3==Add_rd_ungray||
- Add_wr_pluse2==Add_rd_ungray||
- Add_wr_pluse==Add_rd_ungray
- )
- Almost_full <=1;
- else
- Almost_full <=0;
-
-assign Fifo_full =Almost_full;
-
-//
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr <=0;
- else if (Current_state==State_err_end)
- Add_wr <=Add_wr_reg;
- else if (Wr_en&&!Full)
- Add_wr <=Add_wr +1;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_jump_tmp <=0;
- else if (Current_state==State_err_end)
- Add_wr_jump_tmp <=1;
- else
- Add_wr_jump_tmp <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_jump_tmp_pl1 <=0;
- else
- Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_jump <=0;
- else if (Current_state==State_err_end)
- Add_wr_jump <=1;
- else if (Add_wr_jump_tmp_pl1)
- Add_wr_jump <=0;
-
-//
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_en_dl1 <=0;
- else
- Fifo_data_en_dl1 <=Fifo_data_en;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_dl1 <=0;
- else
- Fifo_data_dl1 <=Fifo_data;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_byte3 <=0;
- else if (Current_state==State_byte3&&Fifo_data_en_dl1)
- Fifo_data_byte3 <=Fifo_data_dl1;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_byte2 <=0;
- else if (Current_state==State_byte2&&Fifo_data_en_dl1)
- Fifo_data_byte2 <=Fifo_data_dl1;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_byte1 <=0;
- else if (Current_state==State_byte1&&Fifo_data_en_dl1)
- Fifo_data_byte1 <=Fifo_data_dl1;
-
-always @ (* )
- case (Current_state)
- State_be0:
- Din_tmp
={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
- State_be1:
- Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
- State_be2:
- Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
- State_be3:
- Din_tmp
={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
- default:
- Din_tmp
={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
- endcase
-
-always @ (*)
- if (Current_state==State_be0||Current_state==State_be1||
- Current_state==State_be2||Current_state==State_be3||
- (Current_state==State_byte0&&Fifo_data_en))
- Wr_en_tmp =1;
- else
- Wr_en_tmp =0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Din_tmp_reg <=0;
- else if(Wr_en_tmp)
- Din_tmp_reg <=Din_tmp;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Wr_en_ptr <=0;
- else if(Current_state==State_idle)
- Wr_en_ptr <=0;
- else if(Wr_en_tmp)
- Wr_en_ptr <=1;
-
-//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- begin
- Wr_en <=0;
- Din <=0;
- end
- else if(RX_APPEND_CRC)
- begin
- Wr_en <=Wr_en_tmp;
- Din <=Din_tmp;
- end
- else
- begin
- Wr_en <=Wr_en_tmp&&Wr_en_ptr;
- Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
- end
-
-//this signal for read side to handle the packet number in fifo
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Packet_number_add_tmp <=0;
- else if (Current_state==State_be0||Current_state==State_be1||
- Current_state==State_be2||Current_state==State_be3)
- Packet_number_add_tmp <=1;
- else
- Packet_number_add_tmp <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- begin
- Packet_number_add_tmp_dl1 <=0;
- Packet_number_add_tmp_dl2 <=0;
- end
- else
- begin
- Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
- Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
- end
-
-//Packet_number_add delay to Din[35] is needed to make sure the data have been
wroten to ram.
-//expand to two cycles long almost=16 ns
-//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or
more clock cycles
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Packet_number_add <=0;
- else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
- Packet_number_add <=1;
- else
- Packet_number_add <=0;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-//******************************************************************************
-//domain Clk_SYS,read data from dprom.b-port for read
-//******************************************************************************
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Current_state_SYS <=SYS_idle;
- else
- Current_state_SYS <=Next_state_SYS;
-
-always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
- case (Current_state_SYS)
- SYS_idle:
- if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
- Next_state_SYS =SYS_read;
- else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
- Next_state_SYS =FF_emtpy_err;
- else
- Next_state_SYS =Current_state_SYS;
- SYS_read:
- if (!Rx_mac_rd)
- Next_state_SYS =SYS_pause;
- else if (Dout[35])
- Next_state_SYS =SYS_wait_end;
- else if (Empty)
- Next_state_SYS =FF_emtpy_err;
- else
- Next_state_SYS =Current_state_SYS;
- SYS_pause:
- if (Rx_mac_rd)
- Next_state_SYS =SYS_read;
- else
- Next_state_SYS =Current_state_SYS;
- FF_emtpy_err:
- if (!Empty)
- Next_state_SYS =SYS_read;
- else
- Next_state_SYS =Current_state_SYS;
- SYS_wait_end:
- if (!Rx_mac_rd)
- Next_state_SYS =SYS_idle;
- else
- Next_state_SYS =Current_state_SYS;
- default:
- Next_state_SYS =SYS_idle;
- endcase
-
-
-//gen Rx_mac_ra
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Packet_number_add_dl1 <=0;
- Packet_number_add_dl2 <=0;
- end
- else
- begin
- Packet_number_add_dl1 <=Packet_number_add;
- Packet_number_add_dl2 <=Packet_number_add_dl1;
- end
-assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
-
-always @ (Current_state_SYS or Next_state_SYS)
- if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
- Packet_number_sub =1;
- else
- Packet_number_sub =0;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Packet_number_inFF <=0;
- else if (Packet_number_add_edge&&!Packet_number_sub)
- Packet_number_inFF <=Packet_number_inFF + 1;
- else if
(!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
- Packet_number_inFF <=Packet_number_inFF - 1;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Fifo_data_count <=0;
- else
- Fifo_data_count
<=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Rx_Hwmark_pl <=0;
- Rx_Lwmark_pl <=0;
- end
- else
- begin
- Rx_Hwmark_pl <=Rx_Hwmark;
- Rx_Lwmark_pl <=Rx_Lwmark;
- end
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Rx_mac_ra <=0;
- else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
- Rx_mac_ra <=0;
- else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
- Rx_mac_ra <=1;
-
-
-//control Add_rd signal;
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_rd <=0;
- else if (Current_state_SYS==SYS_read&&!Dout[35])
- Add_rd <=Add_rd + 1;
-
-//
-always @ (posedge Reset or posedge Clk_SYS)
- if (Reset)
- Add_rd_gray <=0;
- else
- begin
- Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
- end
-//
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_wr_gray_dl1 <=0;
- else
- Add_wr_gray_dl1 <=Add_wr_gray;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_wr_jump_rd_pl1 <=0;
- else
- Add_wr_jump_rd_pl1 <=Add_wr_jump;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_wr_ungray =0;
- else if (!Add_wr_jump_rd_pl1)
- begin
- Add_wr_ungray[`MAC_RX_FF_DEPTH-1]
=Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_wr_ungray[i]
=Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
- end
-//empty signal gen
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Empty <=1;
- else if (Add_rd==Add_wr_ungray)
- Empty <=1;
- else
- Empty <=0;
-
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Dout_dl1 <=0;
- else
- Dout_dl1 <=Dout;
-
-assign Rx_mac_data =Dout_dl1[31:0];
-assign Rx_mac_BE =Dout_dl1[33:32];
-assign Rx_mac_eop =Dout_dl1[35];
-
-//aligned to Addr_rd
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Rx_mac_pa_tmp <=0;
- else if (Current_state_SYS==SYS_read&&!Dout[35])
- Rx_mac_pa_tmp <=1;
- else
- Rx_mac_pa_tmp <=0;
-
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Rx_mac_pa <=0;
- else
- Rx_mac_pa <=Rx_mac_pa_tmp;
-
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Rx_mac_sop_tmp <=0;
- else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
- Rx_mac_sop_tmp <=1;
- else
- Rx_mac_sop_tmp <=0;
-
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Rx_mac_sop_tmp_dl1 <=0;
- Rx_mac_sop <=0;
- end
- else
- begin
- Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
- Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
- end
-
-
-
-//******************************************************************************
-
-duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
-.data_a (Din ),
-.wren_a (Wr_en ),
-.address_a (Add_wr ),
-.address_b (Add_rd ),
-.clock_a (Clk_MAC ),
-.clock_b (Clk_SYS ),
-.q_b (Dout ));
-
-endmodule
-
-
-
-
-
+ always @ (posedge Reset or posedge Clk_MAC)
+ if (Reset)
+ Add_wr_gray <=0;
+ else
+ begin
+ Add_wr_gray[MAC_RX_FF_DEPTH-1] <=Add_wr[MAC_RX_FF_DEPTH-1];
+ for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
+ end
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_gray_dl1 <=0;
+ else
+ Add_rd_gray_dl1 <=Add_rd_gray;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_ungray =0;
+ else
+ begin
+ Add_rd_ungray[MAC_RX_FF_DEPTH-1]
=Add_rd_gray_dl1[MAC_RX_FF_DEPTH-1];
+ for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
+ end
+ assign Add_wr_pluse=Add_wr+1;
+ assign Add_wr_pluse4=Add_wr+4;
+ assign Add_wr_pluse3=Add_wr+3;
+ assign Add_wr_pluse2=Add_wr+2;
+
+
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Full <=0;
+ else if (Add_wr_pluse==Add_rd_ungray)
+ Full <=1;
+ else
+ Full <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Almost_full <=0;
+ else if (Add_wr_pluse4==Add_rd_ungray||
+ Add_wr_pluse3==Add_rd_ungray||
+ Add_wr_pluse2==Add_rd_ungray||
+ Add_wr_pluse==Add_rd_ungray
+ )
+ Almost_full <=1;
+ else
+ Almost_full <=0;
+
+ assign Fifo_full =Almost_full;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr <=0;
+ else if (Current_state==State_err_end)
+ Add_wr <=Add_wr_reg;
+ else if (Wr_en&&!Full)
+ Add_wr <=Add_wr +1;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump_tmp <=0;
+ else if (Current_state==State_err_end)
+ Add_wr_jump_tmp <=1;
+ else
+ Add_wr_jump_tmp <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump_tmp_pl1 <=0;
+ else
+ Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump <=0;
+ else if (Current_state==State_err_end)
+ Add_wr_jump <=1;
+ else if (Add_wr_jump_tmp_pl1)
+ Add_wr_jump <=0;
+
+ //
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_en_dl1 <=0;
+ else
+ Fifo_data_en_dl1 <=Fifo_data_en;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_dl1 <=0;
+ else
+ Fifo_data_dl1 <=Fifo_data;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_byte3 <=0;
+ else if (Current_state==State_byte3&&Fifo_data_en_dl1)
+ Fifo_data_byte3 <=Fifo_data_dl1;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_byte2 <=0;
+ else if (Current_state==State_byte2&&Fifo_data_en_dl1)
+ Fifo_data_byte2 <=Fifo_data_dl1;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_byte1 <=0;
+ else if (Current_state==State_byte1&&Fifo_data_en_dl1)
+ Fifo_data_byte1 <=Fifo_data_dl1;
+
+ always @ (* )
+ case (Current_state)
+ State_be0:
+ Din_tmp
={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
+ State_be1:
+ Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
+ State_be2:
+ Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
+ State_be3:
+ Din_tmp
={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
+ default:
+ Din_tmp
={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
+ endcase
+
+ always @ (*)
+ if (Current_state==State_be0||Current_state==State_be1||
+ Current_state==State_be2||Current_state==State_be3||
+ (Current_state==State_byte0&&Fifo_data_en))
+ Wr_en_tmp =1;
+ else
+ Wr_en_tmp =0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Din_tmp_reg <=0;
+ else if(Wr_en_tmp)
+ Din_tmp_reg <=Din_tmp;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Wr_en_ptr <=0;
+ else if(Current_state==State_idle)
+ Wr_en_ptr <=0;
+ else if(Wr_en_tmp)
+ Wr_en_ptr <=1;
+
+ //if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ begin
+ Wr_en <=0;
+ Din <=0;
+ end
+ else if(RX_APPEND_CRC)
+ begin
+ Wr_en <=Wr_en_tmp;
+ Din <=Din_tmp;
+ end
+ else
+ begin
+ Wr_en <=Wr_en_tmp&&Wr_en_ptr;
+ Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
+ end
+
+ //this signal for read side to handle the packet number in fifo
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Packet_number_add_tmp <=0;
+ else if (Current_state==State_be0||Current_state==State_be1||
+ Current_state==State_be2||Current_state==State_be3)
+ Packet_number_add_tmp <=1;
+ else
+ Packet_number_add_tmp <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ begin
+ Packet_number_add_tmp_dl1 <=0;
+ Packet_number_add_tmp_dl2 <=0;
+ end
+ else
+ begin
+ Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
+ Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
+ end
+
+ //Packet_number_add delay to Din[35] is needed to make sure the data have
been wroten to ram.
+ //expand to two cycles long almost=16 ns
+ //if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or
more clock cycles
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Packet_number_add <=0;
+ else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
+ Packet_number_add <=1;
+ else
+ Packet_number_add <=0;
+
+ //
******************************************************************************
+ // domain Clk_SYS,read data from dprom.b-port for read
+ //
******************************************************************************
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Current_state_SYS <=SYS_idle;
+ else
+ Current_state_SYS <=Next_state_SYS;
+
+ always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
+ case (Current_state_SYS)
+ SYS_idle:
+ if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
+ Next_state_SYS =SYS_read;
+ else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
+ Next_state_SYS =FF_emtpy_err;
+ else
+ Next_state_SYS =Current_state_SYS;
+ SYS_read:
+ if (!Rx_mac_rd)
+ Next_state_SYS =SYS_pause;
+ else if (Dout[35])
+ Next_state_SYS =SYS_wait_end;
+ else if (Empty)
+ Next_state_SYS =FF_emtpy_err;
+ else
+ Next_state_SYS =Current_state_SYS;
+ SYS_pause:
+ if (Rx_mac_rd)
+ Next_state_SYS =SYS_read;
+ else
+ Next_state_SYS =Current_state_SYS;
+ FF_emtpy_err:
+ if (!Empty)
+ Next_state_SYS =SYS_read;
+ else
+ Next_state_SYS =Current_state_SYS;
+ SYS_wait_end:
+ if (!Rx_mac_rd)
+ Next_state_SYS =SYS_idle;
+ else
+ Next_state_SYS =Current_state_SYS;
+ default:
+ Next_state_SYS =SYS_idle;
+ endcase // case(Current_state_SYS)
+
+ //gen Rx_mac_ra
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Packet_number_add_dl1 <=0;
+ Packet_number_add_dl2 <=0;
+ end
+ else
+ begin
+ Packet_number_add_dl1 <=Packet_number_add;
+ Packet_number_add_dl2 <=Packet_number_add_dl1;
+ end
+ assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
+
+ always @ (Current_state_SYS or Next_state_SYS)
+ if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
+ Packet_number_sub =1;
+ else
+ Packet_number_sub =0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Packet_number_inFF <=0;
+ else if (Packet_number_add_edge&&!Packet_number_sub)
+ Packet_number_inFF <=Packet_number_inFF + 1;
+ else if
(!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
+ Packet_number_inFF <=Packet_number_inFF - 1;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Fifo_data_count <=0;
+ else
+ Fifo_data_count
<=Add_wr_ungray[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5]-Add_rd[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5];
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Rx_Hwmark_pl <=0;
+ Rx_Lwmark_pl <=0;
+ end
+ else
+ begin
+ Rx_Hwmark_pl <=Rx_Hwmark;
+ Rx_Lwmark_pl <=Rx_Lwmark;
+ end
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Rx_mac_ra <=0;
+ else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
+ Rx_mac_ra <=0;
+ else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
+ Rx_mac_ra <=1;
+
+
+ //control Add_rd signal;
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_rd <=0;
+ else if (Current_state_SYS==SYS_read&&!Dout[35])
+ Add_rd <=Add_rd + 1;
+
+ //
+ always @ (posedge Reset or posedge Clk_SYS)
+ if (Reset)
+ Add_rd_gray <=0;
+ else
+ begin
+ Add_rd_gray[MAC_RX_FF_DEPTH-1] <=Add_rd[MAC_RX_FF_DEPTH-1];
+ for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
+ end
+ //
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_wr_gray_dl1 <=0;
+ else
+ Add_wr_gray_dl1 <=Add_wr_gray;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_wr_jump_rd_pl1 <=0;
+ else
+ Add_wr_jump_rd_pl1 <=Add_wr_jump;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_wr_ungray =0;
+ else if (!Add_wr_jump_rd_pl1)
+ begin
+ Add_wr_ungray[MAC_RX_FF_DEPTH-1]
=Add_wr_gray_dl1[MAC_RX_FF_DEPTH-1];
+ for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
+ end
+ //empty signal gen
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Empty <=1;
+ else if (Add_rd==Add_wr_ungray)
+ Empty <=1;
+ else
+ Empty <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Dout_dl1 <=0;
+ else
+ Dout_dl1 <=Dout;
+
+ assign Rx_mac_data =Dout_dl1[31:0];
+ assign Rx_mac_BE =Dout_dl1[33:32];
+ assign Rx_mac_eop =Dout_dl1[35];
+
+ //aligned to Addr_rd
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Rx_mac_pa_tmp <=0;
+ else if (Current_state_SYS==SYS_read&&!Dout[35])
+ Rx_mac_pa_tmp <=1;
+ else
+ Rx_mac_pa_tmp <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Rx_mac_pa <=0;
+ else
+ Rx_mac_pa <=Rx_mac_pa_tmp;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Rx_mac_sop_tmp <=0;
+ else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
+ Rx_mac_sop_tmp <=1;
+ else
+ Rx_mac_sop_tmp <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Rx_mac_sop_tmp_dl1 <=0;
+ Rx_mac_sop <=0;
+ end
+ else
+ begin
+ Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
+ Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
+ end
+
+
//******************************************************************************
+
+ duram #(36,MAC_RX_FF_DEPTH)
+ U_duram(.data_a (Din ),
+ .wren_a (Wr_en ),
+ .address_a (Add_wr ),
+ .address_b (Add_rd ),
+ .clock_a (Clk_MAC ),
+ .clock_b (Clk_SYS ),
+ .q_b (Dout ));
+
+endmodule // MAC_rx_FF
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -156,30 +156,30 @@
.RX_MIN_LENGTH (RX_MIN_LENGTH )
);
-MAC_rx_FF U_MAC_rx_FF (
-.Reset (Reset ),
-.Clk_MAC (Clk ),
-.Clk_SYS (Clk_user ),
- //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),
-.Fifo_data (Fifo_data ),
-.Fifo_data_en (Fifo_data_en ),
-.Fifo_full (Fifo_full ),
-.Fifo_data_err (Fifo_data_err ),
-.Fifo_data_end (Fifo_data_end ),
- //CPU (//CPU ),
-.Rx_Hwmark (Rx_Hwmark ),
-.Rx_Lwmark (Rx_Lwmark ),
-.RX_APPEND_CRC (RX_APPEND_CRC ),
- //user interface (//user interface ),
-.Rx_mac_ra (Rx_mac_ra ),
-.Rx_mac_rd (Rx_mac_rd ),
-.Rx_mac_data (Rx_mac_data ),
-.Rx_mac_BE (Rx_mac_BE ),
-.Rx_mac_sop (Rx_mac_sop ),
-.Rx_mac_pa (Rx_mac_pa ),
-.Rx_mac_eop (Rx_mac_eop )
-);
-
+MAC_rx_FF #(.MAC_RX_FF_DEPTH(9))
+ U_MAC_rx_FF (.Reset (Reset ),
+ .Clk_MAC (Clk ),
+ .Clk_SYS (Clk_user ),
+ //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),
+ .Fifo_data (Fifo_data ),
+ .Fifo_data_en (Fifo_data_en ),
+ .Fifo_full (Fifo_full ),
+ .Fifo_data_err (Fifo_data_err ),
+ .Fifo_data_end (Fifo_data_end ),
+ //CPU (//CPU ),
+ .Rx_Hwmark (Rx_Hwmark ),
+ .Rx_Lwmark (Rx_Lwmark ),
+ .RX_APPEND_CRC (RX_APPEND_CRC ),
+ //user interface (//user interface ),
+ .Rx_mac_ra (Rx_mac_ra ),
+ .Rx_mac_rd (Rx_mac_rd ),
+ .Rx_mac_data (Rx_mac_data ),
+ .Rx_mac_BE (Rx_mac_BE ),
+ .Rx_mac_sop (Rx_mac_sop ),
+ .Rx_mac_pa (Rx_mac_pa ),
+ .Rx_mac_eop (Rx_mac_eop )
+ );
+
`ifdef MAC_BROADCAST_FILTER_EN
Broadcast_filter U_Broadcast_filter(
.Reset (Reset ),
@@ -227,4 +227,4 @@
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -346,7 +346,7 @@
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));
-Reg_int U_Reg_int(
+reg_int U_reg_int(
.Reset (Reset ),
.Clk_reg (Clk_reg ),
.CSB (CSB ),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,7 +1,7 @@
/CRC_gen.v/1.3/Thu Jan 19 14:07:54 2006//
-/MAC_tx_Ctrl.v/1.4/Sun Jun 25 04:58:56 2006//
-/MAC_tx_FF.v/1.5/Sun Jun 25 04:58:56 2006//
/MAC_tx_addr_add.v/1.3/Thu Jan 19 14:07:54 2006//
-/Ramdon_gen.v/1.3/Thu Jan 19 14:07:54 2006//
/flow_ctrl.v/1.3/Thu Jan 19 14:07:54 2006//
+/MAC_tx_FF.v/1.5/Tue May 1 07:35:17 2007//
+/MAC_tx_Ctrl.v/1.4/Wed May 2 06:49:15 2007//
+/Ramdon_gen.v/1.3/Wed May 2 06:49:15 2007//
D
Deleted:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -59,735 +59,687 @@
// no message
//
-module MAC_tx_FF (
-Reset ,
-Clk_MAC ,
-Clk_SYS ,
-//MAC_rx_ctrl interface
-Fifo_data ,
-Fifo_rd ,
-Fifo_rd_finish ,
-Fifo_rd_retry ,
-Fifo_eop ,
-Fifo_da ,
-Fifo_ra ,
-Fifo_data_err_empty ,
-Fifo_data_err_full ,
-//user interface
-Tx_mac_wa ,
-Tx_mac_wr ,
-Tx_mac_data ,
-Tx_mac_BE ,
-Tx_mac_sop ,
-Tx_mac_eop ,
-//host interface
-FullDuplex ,
-Tx_Hwmark ,
-Tx_Lwmark
+module MAC_tx_FF
+ #(parameter MAC_TX_FF_DEPTH = 9)
+ (Reset ,
+ Clk_MAC ,
+ Clk_SYS ,
+ //MAC_rx_ctrl interface
+ Fifo_data ,
+ Fifo_rd ,
+ Fifo_rd_finish ,
+ Fifo_rd_retry ,
+ Fifo_eop ,
+ Fifo_da ,
+ Fifo_ra ,
+ Fifo_data_err_empty ,
+ Fifo_data_err_full ,
+ //user interface
+ Tx_mac_wa ,
+ Tx_mac_wr ,
+ Tx_mac_data ,
+ Tx_mac_BE ,
+ Tx_mac_sop ,
+ Tx_mac_eop ,
+ //host interface
+ FullDuplex ,
+ Tx_Hwmark ,
+ Tx_Lwmark);
+
+ input Reset ;
+ input Clk_MAC ;
+ input Clk_SYS ;
+ //MAC_tx_ctrl
+ output [7:0] Fifo_data ;
+ input Fifo_rd ;
+ input Fifo_rd_finish ;
+ input Fifo_rd_retry ;
+ output Fifo_eop ;
+ output Fifo_da ;
+ output Fifo_ra ;
+ output Fifo_data_err_empty ;
+ output Fifo_data_err_full ;
+ //user interface
+ output Tx_mac_wa ;
+ input Tx_mac_wr ;
+ input [31:0] Tx_mac_data ;
+ input [1:0] Tx_mac_BE ;//big endian
+ input Tx_mac_sop ;
+ input Tx_mac_eop ;
+ //host interface
+ input FullDuplex ;
+ input [4:0] Tx_Hwmark ;
+ input [4:0] Tx_Lwmark ;
+ //
******************************************************************************
+ //internal signals
+ //
******************************************************************************
+ parameter MAC_byte3 =4'd00;
+ parameter MAC_byte2 =4'd01;
+ parameter MAC_byte1 =4'd02;
+ parameter MAC_byte0 =4'd03;
+ parameter MAC_wait_finish =4'd04;
+ parameter MAC_retry =4'd08;
+ parameter MAC_idle =4'd09;
+ parameter MAC_FFEmpty =4'd10;
+ parameter MAC_FFEmpty_drop =4'd11;
+ parameter MAC_pkt_sub =4'd12;
+ parameter MAC_FF_Err =4'd13;
+
+ reg [3:0] Current_state_MAC /* synthesis syn_preserve =1 */
;
+ reg [3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */
;
+ reg [3:0] Next_state_MAC ;
+
+ parameter SYS_idle =4'd0;
+ parameter SYS_WaitSop =4'd1;
+ parameter SYS_SOP =4'd2;
+ parameter SYS_MOP =4'd3;
+ parameter SYS_DROP =4'd4;
+ parameter SYS_EOP_ok =4'd5;
+ parameter SYS_FFEmpty =4'd6;
+ parameter SYS_EOP_err =4'd7;
+ parameter SYS_SOP_err =4'd8;
+
+ reg [3:0] Current_state_SYS /* synthesis syn_preserve =1 */;
+ reg [3:0] Next_state_SYS;
+
+ reg [MAC_TX_FF_DEPTH-1:0] Add_wr ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_wr_ungray ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_wr_gray ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1 ;
+ wire [MAC_TX_FF_DEPTH-1:0] Add_wr_gray_tmp ;
+
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd_reg ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd_gray ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1 ;
+ wire [MAC_TX_FF_DEPTH-1:0] Add_rd_gray_tmp ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd_ungray ;
+ wire [35:0] Din ;
+ wire [35:0] Dout ;
+ reg Wr_en ;
+ wire [MAC_TX_FF_DEPTH-1:0] Add_wr_pluse ;
+ wire [MAC_TX_FF_DEPTH-1:0] Add_wr_pluse_pluse;
+ wire [MAC_TX_FF_DEPTH-1:0] Add_rd_pluse ;
+ reg [MAC_TX_FF_DEPTH-1:0] Add_rd_reg_dl1 ;
+ reg Full /* synthesis syn_keep=1
*/;
+ reg AlmostFull /* synthesis syn_keep=1
*/;
+ reg Empty /* synthesis syn_keep=1
*/;
+
+ reg Tx_mac_wa ;
+ reg Tx_mac_wr_dl1 ;
+ reg [31:0] Tx_mac_data_dl1 ;
+ reg [1:0] Tx_mac_BE_dl1 ;
+ reg Tx_mac_sop_dl1 ;
+ reg Tx_mac_eop_dl1 ;
+ reg FF_FullErr ;
+ wire [1:0] Dout_BE ;
+ wire Dout_eop ;
+ wire Dout_err ;
+ wire [31:0] Dout_data ;
+ reg [35:0] Dout_reg /* synthesis
syn_preserve=1 */;
+ reg Packet_number_sub_dl1 ;
+ reg Packet_number_sub_dl2 ;
+ reg Packet_number_sub_edge /* synthesis
syn_preserve=1 */;
+ reg Packet_number_add /* synthesis
syn_preserve=1 */;
+ reg [4:0] Fifo_data_count ;
+ reg Fifo_ra /* synthesis
syn_keep=1 */;
+ reg [7:0] Fifo_data ;
+ reg Fifo_da ;
+ reg Fifo_data_err_empty /* synthesis
syn_preserve=1 */;
+ reg Fifo_eop ;
+ reg Fifo_rd_dl1 ;
+ reg Fifo_ra_tmp ;
+ reg [5:0] Packet_number_inFF /* synthesis syn_keep=1
*/;
+ reg [5:0] Packet_number_inFF_reg /* synthesis
syn_preserve=1 */;
+ reg Pkt_sub_apply_tmp ;
+ reg Pkt_sub_apply ;
+ reg Add_rd_reg_rdy_tmp ;
+ reg Add_rd_reg_rdy ;
+ reg Add_rd_reg_rdy_dl1 ;
+ reg Add_rd_reg_rdy_dl2 ;
+ reg [4:0] Tx_Hwmark_pl ;
+ reg [4:0] Tx_Lwmark_pl ;
+ reg Add_rd_jump_tmp ;
+ reg Add_rd_jump_tmp_pl1 ;
+ reg Add_rd_jump ;
+ reg Add_rd_jump_wr_pl1 ;
+
+ integer i ;
-);
-input Reset ;
-input Clk_MAC ;
-input Clk_SYS ;
- //MAC_tx_ctrl
-output [7:0] Fifo_data ;
-input Fifo_rd ;
-input Fifo_rd_finish ;
-input Fifo_rd_retry ;
-output Fifo_eop ;
-output Fifo_da ;
-output Fifo_ra ;
-output Fifo_data_err_empty ;
-output Fifo_data_err_full ;
- //user interface
-output Tx_mac_wa ;
-input Tx_mac_wr ;
-input [31:0] Tx_mac_data ;
-input [1:0] Tx_mac_BE ;//big endian
-input Tx_mac_sop ;
-input Tx_mac_eop ;
- //host interface
-input FullDuplex ;
-input [4:0] Tx_Hwmark ;
-input [4:0] Tx_Lwmark ;
-//******************************************************************************
-//internal signals
-//******************************************************************************
-parameter MAC_byte3 =4'd00;
-parameter MAC_byte2 =4'd01;
-parameter MAC_byte1 =4'd02;
-parameter MAC_byte0 =4'd03;
-parameter MAC_wait_finish =4'd04;
-parameter MAC_retry =4'd08;
-parameter MAC_idle =4'd09;
-parameter MAC_FFEmpty =4'd10;
-parameter MAC_FFEmpty_drop =4'd11;
-parameter MAC_pkt_sub =4'd12;
-parameter MAC_FF_Err =4'd13;
+ //
******************************************************************************
+ //write data to from FF .
+ //domain Clk_SYS
+ //
******************************************************************************
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Current_state_SYS <=SYS_idle;
+ else
+ Current_state_SYS <=Next_state_SYS;
+
+ always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or
AlmostFull
+ or Tx_mac_eop )
+ case (Current_state_SYS)
+ SYS_idle:
+ if (Tx_mac_wr&&Tx_mac_sop&&!Full)
+ Next_state_SYS =SYS_SOP;
+ else
+ Next_state_SYS =Current_state_SYS ;
+ SYS_SOP:
+ Next_state_SYS =SYS_MOP;
+ SYS_MOP:
+ if (AlmostFull)
+ Next_state_SYS =SYS_DROP;
+ else if (Tx_mac_wr&&Tx_mac_sop)
+ Next_state_SYS =SYS_SOP_err;
+ else if (Tx_mac_wr&&Tx_mac_eop)
+ Next_state_SYS =SYS_EOP_ok;
+ else
+ Next_state_SYS =Current_state_SYS ;
+ SYS_EOP_ok:
+ if (Tx_mac_wr&&Tx_mac_sop)
+ Next_state_SYS =SYS_SOP;
+ else
+ Next_state_SYS =SYS_idle;
+ SYS_EOP_err:
+ if (Tx_mac_wr&&Tx_mac_sop)
+ Next_state_SYS =SYS_SOP;
+ else
+ Next_state_SYS =SYS_idle;
+ SYS_SOP_err:
+ Next_state_SYS =SYS_DROP;
+ SYS_DROP: //FIFO overflow
+ if (Tx_mac_wr&&Tx_mac_eop)
+ Next_state_SYS =SYS_EOP_err;
+ else
+ Next_state_SYS =Current_state_SYS ;
+ default:
+ Next_state_SYS =SYS_idle;
+ endcase
+
+ //delay signals
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Tx_mac_wr_dl1 <=0;
+ Tx_mac_data_dl1 <=0;
+ Tx_mac_BE_dl1 <=0;
+ Tx_mac_sop_dl1 <=0;
+ Tx_mac_eop_dl1 <=0;
+ end
+ else
+ begin
+ Tx_mac_wr_dl1 <=Tx_mac_wr ;
+ Tx_mac_data_dl1 <=Tx_mac_data ;
+ Tx_mac_BE_dl1 <=Tx_mac_BE ;
+ Tx_mac_sop_dl1 <=Tx_mac_sop ;
+ Tx_mac_eop_dl1 <=Tx_mac_eop ;
+ end
+
+ always @(Current_state_SYS)
+ if (Current_state_SYS==SYS_EOP_err)
+ FF_FullErr =1;
+ else
+ FF_FullErr =0;
+
+ reg Tx_mac_eop_gen;
+
+ always @(Current_state_SYS)
+ if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok)
+ Tx_mac_eop_gen =1;
+ else
+ Tx_mac_eop_gen =0;
+
+ assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1};
+
+ always @(Current_state_SYS or Tx_mac_wr_dl1)
+ if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok||
+
Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1)
+ Wr_en = 1;
+ else
+ Wr_en = 0;
+
+
+ always @ (posedge Reset or posedge Clk_SYS)
+ if (Reset)
+ Add_wr_gray <=0;
+ else
+ begin
+ Add_wr_gray[MAC_TX_FF_DEPTH-1] <=Add_wr[MAC_TX_FF_DEPTH-1];
+ for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
+ end
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_rd_gray_dl1 <=0;
+ else
+ Add_rd_gray_dl1 <=Add_rd_gray;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_rd_jump_wr_pl1 <=0;
+ else
+ Add_rd_jump_wr_pl1 <=Add_rd_jump;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_rd_ungray =0;
+ else if (!Add_rd_jump_wr_pl1)
+ begin
+ Add_rd_ungray[MAC_TX_FF_DEPTH-1]
=Add_rd_gray_dl1[MAC_TX_FF_DEPTH-1];
+ for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
+ end
+ assign Add_wr_pluse =Add_wr+1;
+ assign Add_wr_pluse_pluse =Add_wr+4;
+
+ always @ (Add_wr_pluse or Add_rd_ungray)
+ if (Add_wr_pluse==Add_rd_ungray)
+ Full =1;
+ else
+ Full =0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ AlmostFull <=0;
+ else if (Add_wr_pluse_pluse==Add_rd_ungray)
+ AlmostFull <=1;
+ else
+ AlmostFull <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_wr <= 0;
+ else if (Wr_en&&!Full)
+ Add_wr <= Add_wr +1;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Packet_number_sub_dl1 <=0;
+ Packet_number_sub_dl2 <=0;
+ end
+ else
+ begin
+ Packet_number_sub_dl1 <=Pkt_sub_apply;
+ Packet_number_sub_dl2 <=Packet_number_sub_dl1;
+ end
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Packet_number_sub_edge <=0;
+ else if (Packet_number_sub_dl1&!Packet_number_sub_dl2)
+ Packet_number_sub_edge <=1;
+ else
+ Packet_number_sub_edge <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Packet_number_add <=0;
+ else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err)
+ Packet_number_add <=1;
+ else
+ Packet_number_add <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Packet_number_inFF <=0;
+ else if (Packet_number_add&&!Packet_number_sub_edge)
+ Packet_number_inFF <=Packet_number_inFF + 1'b1;
+ else if (!Packet_number_add&&Packet_number_sub_edge)
+ Packet_number_inFF <=Packet_number_inFF - 1'b1;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Packet_number_inFF_reg <=0;
+ else
+ Packet_number_inFF_reg <=Packet_number_inFF;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Add_rd_reg_rdy_dl1 <=0;
+ Add_rd_reg_rdy_dl2 <=0;
+ end
+ else
+ begin
+ Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy;
+ Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1;
+ end
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_rd_reg_dl1 <=0;
+ else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2)
+ Add_rd_reg_dl1 <=Add_rd_reg;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Fifo_data_count <=0;
+ else if (FullDuplex)
+ Fifo_data_count
<=Add_wr[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]-Add_rd_ungray[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5];
+ else
+ Fifo_data_count
<=Add_wr[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]-Add_rd_reg_dl1[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5];
//for half duplex backoff requirement
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Fifo_ra_tmp <=0;
+ else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark)
+ Fifo_ra_tmp <=1;
+ else
+ Fifo_ra_tmp <=0;
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ begin
+ Tx_Hwmark_pl <=0;
+ Tx_Lwmark_pl <=0;
+ end
+ else
+ begin
+ Tx_Hwmark_pl <=Tx_Hwmark;
+ Tx_Lwmark_pl <=Tx_Lwmark;
+ end
+
+ always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Tx_mac_wa <=0;
+ else if (Fifo_data_count>=Tx_Hwmark_pl)
+ Tx_mac_wa <=0;
+ else if (Fifo_data_count<Tx_Lwmark_pl)
+ Tx_mac_wa <=1;
+
+ //
******************************************************************************
+ // rd data to from FF .
+ // domain Clk_MAC
+ //
******************************************************************************
+ reg[35:0] Dout_dl1;
+ reg Dout_reg_en /* synthesis syn_keep=1 */;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Dout_dl1 <=0;
+ else
+ Dout_dl1 <=Dout;
+
+ always @ (Current_state_MAC or Next_state_MAC)
+ if
((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
+ Dout_reg_en =1;
+ else
+ Dout_reg_en =0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Dout_reg <=0;
+ else if (Dout_reg_en)
+ Dout_reg <=Dout_dl1;
+
+ assign {Dout_eop,Dout_err,Dout_BE,Dout_data}=Dout_reg;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Current_state_MAC <=MAC_idle;
+ else
+ Current_state_MAC <=Next_state_MAC;
+
+ always @ (Current_state_MAC or Fifo_rd or Dout_BE or Dout_eop or
Fifo_rd_retry
+ or Fifo_rd_finish or Empty or Fifo_rd or Fifo_eop)
+ case (Current_state_MAC)
+ MAC_idle:
+ if (Empty&&Fifo_rd)
+ Next_state_MAC=MAC_FF_Err;
+ else if (Fifo_rd)
+ Next_state_MAC=MAC_byte3;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_byte3:
+ if (Fifo_rd_retry)
+ Next_state_MAC=MAC_retry;
+ else if (Fifo_eop)
+ Next_state_MAC=MAC_wait_finish;
+ else if (Fifo_rd&&!Fifo_eop)
+ Next_state_MAC=MAC_byte2;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_byte2:
+ if (Fifo_rd_retry)
+ Next_state_MAC=MAC_retry;
+ else if (Fifo_eop)
+ Next_state_MAC=MAC_wait_finish;
+ else if (Fifo_rd&&!Fifo_eop)
+ Next_state_MAC=MAC_byte1;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_byte1:
+ if (Fifo_rd_retry)
+ Next_state_MAC=MAC_retry;
+ else if (Fifo_eop)
+ Next_state_MAC=MAC_wait_finish;
+ else if (Fifo_rd&&!Fifo_eop)
+ Next_state_MAC=MAC_byte0;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_byte0:
+ if (Empty&&Fifo_rd&&!Fifo_eop)
+ Next_state_MAC=MAC_FFEmpty;
+ else if (Fifo_rd_retry)
+ Next_state_MAC=MAC_retry;
+ else if (Fifo_eop)
+ Next_state_MAC=MAC_wait_finish;
+ else if (Fifo_rd&&!Fifo_eop)
+ Next_state_MAC=MAC_byte3;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_retry:
+ Next_state_MAC=MAC_idle;
+ MAC_wait_finish:
+ if (Fifo_rd_finish)
+ Next_state_MAC=MAC_pkt_sub;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_pkt_sub:
+ Next_state_MAC=MAC_idle;
+ MAC_FFEmpty:
+ if (!Empty)
+ Next_state_MAC=MAC_byte3;
+ else
+ Next_state_MAC=Current_state_MAC;
+ MAC_FF_Err: //stopped state-machine need change
+ Next_state_MAC=Current_state_MAC;
+ default
+ Next_state_MAC=MAC_idle;
+ endcase
-reg [3:0] Current_state_MAC /* synthesis syn_preserve =1 */ ;
-reg [3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */ ;
-reg [3:0] Next_state_MAC ;
+ always @ (posedge Reset or posedge Clk_MAC)
+ if (Reset)
+ Add_rd_gray <=0;
+ else
+ begin
+ Add_rd_gray[MAC_TX_FF_DEPTH-1] <=Add_rd[MAC_TX_FF_DEPTH-1];
+ for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
+ end
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_gray_dl1 <=0;
+ else
+ Add_wr_gray_dl1 <=Add_wr_gray;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_ungray =0;
+ else
+ begin
+ Add_wr_ungray[MAC_TX_FF_DEPTH-1]
=Add_wr_gray_dl1[MAC_TX_FF_DEPTH-1];
+ for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1)
+ Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
+ end
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Empty <=1;
+ else if (Add_rd==Add_wr_ungray)
+ Empty <=1;
+ else
+ Empty <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_ra <=0;
+ else
+ Fifo_ra <=Fifo_ra_tmp;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Pkt_sub_apply_tmp <=0;
+ else if (Current_state_MAC==MAC_pkt_sub)
+ Pkt_sub_apply_tmp <=1;
+ else
+ Pkt_sub_apply_tmp <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Pkt_sub_apply <=0;
+ else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp)
+ Pkt_sub_apply <=1;
+ else
+ Pkt_sub_apply <=0;
+
+ //reg Add_rd for collison retry
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_reg <=0;
+ else if (Fifo_rd_finish)
+ Add_rd_reg <=Add_rd;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_reg_rdy_tmp <=0;
+ else if (Fifo_rd_finish)
+ Add_rd_reg_rdy_tmp <=1;
+ else
+ Add_rd_reg_rdy_tmp <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_reg_rdy <=0;
+ else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp)
+ Add_rd_reg_rdy <=1;
+ else
+ Add_rd_reg_rdy <=0;
+
+ reg Add_rd_add /* synthesis syn_keep=1 */;
+
+ always @ (Current_state_MAC or Next_state_MAC)
+ if
((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
+ Add_rd_add =1;
+ else
+ Add_rd_add =0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd <=0;
+ else if (Current_state_MAC==MAC_retry)
+ Add_rd <= Add_rd_reg;
+ else if (Add_rd_add)
+ Add_rd <= Add_rd + 1;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_jump_tmp <=0;
+ else if (Current_state_MAC==MAC_retry)
+ Add_rd_jump_tmp <=1;
+ else
+ Add_rd_jump_tmp <=0;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_jump_tmp_pl1 <=0;
+ else
+ Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_rd_jump <=0;
+ else if (Current_state_MAC==MAC_retry)
+ Add_rd_jump <=1;
+ else if (Add_rd_jump_tmp_pl1)
+ Add_rd_jump <=0;
+
+ //gen Fifo_data
+ always @ (Dout_data or Current_state_MAC)
+ case (Current_state_MAC)
+ MAC_byte3:
+ Fifo_data =Dout_data[31:24];
+ MAC_byte2:
+ Fifo_data =Dout_data[23:16];
+ MAC_byte1:
+ Fifo_data =Dout_data[15:8];
+ MAC_byte0:
+ Fifo_data =Dout_data[7:0];
+ default:
+ Fifo_data =0;
+ endcase
-parameter SYS_idle =4'd0;
-parameter SYS_WaitSop =4'd1;
-parameter SYS_SOP =4'd2;
-parameter SYS_MOP =4'd3;
-parameter SYS_DROP =4'd4;
-parameter SYS_EOP_ok =4'd5;
-parameter SYS_FFEmpty =4'd6;
-parameter SYS_EOP_err =4'd7;
-parameter SYS_SOP_err =4'd8;
-
-reg [3:0] Current_state_SYS /* synthesis syn_preserve =1 */;
-reg [3:0] Next_state_SYS;
-
-reg [`MAC_RX_FF_DEPTH-1:0] Add_wr ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1 ;
-wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_tmp ;
-
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1 ;
-wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_tmp ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray ;
-wire[35:0] Din ;
-wire[35:0] Dout ;
-reg Wr_en ;
-wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse ;
-wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse_pluse;
-wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_pluse ;
-reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg_dl1 ;
-reg Full /* synthesis syn_keep=1 */;
-reg AlmostFull /* synthesis syn_keep=1 */;
-reg Empty /* synthesis syn_keep=1 */;
-
-reg Tx_mac_wa ;
-reg Tx_mac_wr_dl1 ;
-reg [31:0] Tx_mac_data_dl1 ;
-reg [1:0] Tx_mac_BE_dl1 ;
-reg Tx_mac_sop_dl1 ;
-reg Tx_mac_eop_dl1 ;
-reg FF_FullErr ;
-wire[1:0] Dout_BE ;
-wire Dout_eop ;
-wire Dout_err ;
-wire[31:0] Dout_data ;
-reg [35:0] Dout_reg /* synthesis syn_preserve=1 */;
-reg Packet_number_sub_dl1 ;
-reg Packet_number_sub_dl2 ;
-reg Packet_number_sub_edge /* synthesis syn_preserve=1 */;
-reg Packet_number_add /* synthesis syn_preserve=1 */;
-reg [4:0] Fifo_data_count ;
-reg Fifo_ra /* synthesis syn_keep=1 */;
-reg [7:0] Fifo_data ;
-reg Fifo_da ;
-reg Fifo_data_err_empty /* synthesis syn_preserve=1 */;
-reg Fifo_eop ;
-reg Fifo_rd_dl1 ;
-reg Fifo_ra_tmp ;
-reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
-reg [5:0] Packet_number_inFF_reg /* synthesis syn_preserve=1 */;
-reg Pkt_sub_apply_tmp ;
-reg Pkt_sub_apply ;
-reg Add_rd_reg_rdy_tmp ;
-reg Add_rd_reg_rdy ;
-reg Add_rd_reg_rdy_dl1 ;
-reg Add_rd_reg_rdy_dl2 ;
-reg [4:0] Tx_Hwmark_pl ;
-reg [4:0] Tx_Lwmark_pl ;
-reg Add_rd_jump_tmp ;
-reg Add_rd_jump_tmp_pl1 ;
-reg Add_rd_jump ;
-reg Add_rd_jump_wr_pl1 ;
-
-integer i ;
-//******************************************************************************
-//write data to from FF .
-//domain Clk_SYS
-//******************************************************************************
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Current_state_SYS <=SYS_idle;
- else
- Current_state_SYS <=Next_state_SYS;
-
-always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull
- or Tx_mac_eop )
- case (Current_state_SYS)
- SYS_idle:
- if (Tx_mac_wr&&Tx_mac_sop&&!Full)
- Next_state_SYS =SYS_SOP;
- else
- Next_state_SYS =Current_state_SYS ;
- SYS_SOP:
- Next_state_SYS =SYS_MOP;
- SYS_MOP:
- if (AlmostFull)
- Next_state_SYS =SYS_DROP;
- else if (Tx_mac_wr&&Tx_mac_sop)
- Next_state_SYS =SYS_SOP_err;
- else if (Tx_mac_wr&&Tx_mac_eop)
- Next_state_SYS =SYS_EOP_ok;
- else
- Next_state_SYS =Current_state_SYS ;
- SYS_EOP_ok:
- if (Tx_mac_wr&&Tx_mac_sop)
- Next_state_SYS =SYS_SOP;
- else
- Next_state_SYS =SYS_idle;
- SYS_EOP_err:
- if (Tx_mac_wr&&Tx_mac_sop)
- Next_state_SYS =SYS_SOP;
- else
- Next_state_SYS =SYS_idle;
- SYS_SOP_err:
- Next_state_SYS =SYS_DROP;
- SYS_DROP: //FIFO overflow
- if (Tx_mac_wr&&Tx_mac_eop)
- Next_state_SYS =SYS_EOP_err;
- else
- Next_state_SYS =Current_state_SYS ;
- default:
- Next_state_SYS =SYS_idle;
- endcase
-
-//delay signals
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Tx_mac_wr_dl1 <=0;
- Tx_mac_data_dl1 <=0;
- Tx_mac_BE_dl1 <=0;
- Tx_mac_sop_dl1 <=0;
- Tx_mac_eop_dl1 <=0;
- end
- else
- begin
- Tx_mac_wr_dl1 <=Tx_mac_wr ;
- Tx_mac_data_dl1 <=Tx_mac_data ;
- Tx_mac_BE_dl1 <=Tx_mac_BE ;
- Tx_mac_sop_dl1 <=Tx_mac_sop ;
- Tx_mac_eop_dl1 <=Tx_mac_eop ;
- end
-
-always @(Current_state_SYS)
- if (Current_state_SYS==SYS_EOP_err)
- FF_FullErr =1;
- else
- FF_FullErr =0;
-
-reg Tx_mac_eop_gen;
-
-always @(Current_state_SYS)
- if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok)
- Tx_mac_eop_gen =1;
- else
- Tx_mac_eop_gen =0;
-
-assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1};
-
-always @(Current_state_SYS or Tx_mac_wr_dl1)
- if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok||
-
Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1)
- Wr_en = 1;
- else
- Wr_en = 0;
-
-
-//
-
-
-always @ (posedge Reset or posedge Clk_SYS)
- if (Reset)
- Add_wr_gray <=0;
- else
- begin
- Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
- end
-
-//
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_rd_gray_dl1 <=0;
- else
- Add_rd_gray_dl1 <=Add_rd_gray;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_rd_jump_wr_pl1 <=0;
- else
- Add_rd_jump_wr_pl1 <=Add_rd_jump;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_rd_ungray =0;
- else if (!Add_rd_jump_wr_pl1)
- begin
- Add_rd_ungray[`MAC_RX_FF_DEPTH-1]
=Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_rd_ungray[i]
=Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
- end
-assign Add_wr_pluse =Add_wr+1;
-assign Add_wr_pluse_pluse =Add_wr+4;
-
-always @ (Add_wr_pluse or Add_rd_ungray)
- if (Add_wr_pluse==Add_rd_ungray)
- Full =1;
- else
- Full =0;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- AlmostFull <=0;
- else if (Add_wr_pluse_pluse==Add_rd_ungray)
- AlmostFull <=1;
- else
- AlmostFull <=0;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_wr <= 0;
- else if (Wr_en&&!Full)
- Add_wr <= Add_wr +1;
-
-
-//
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Packet_number_sub_dl1 <=0;
- Packet_number_sub_dl2 <=0;
- end
- else
- begin
- Packet_number_sub_dl1 <=Pkt_sub_apply;
- Packet_number_sub_dl2 <=Packet_number_sub_dl1;
- end
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Packet_number_sub_edge <=0;
- else if (Packet_number_sub_dl1&!Packet_number_sub_dl2)
- Packet_number_sub_edge <=1;
- else
- Packet_number_sub_edge <=0;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Packet_number_add <=0;
- else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err)
- Packet_number_add <=1;
- else
- Packet_number_add <=0;
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Packet_number_inFF <=0;
- else if (Packet_number_add&&!Packet_number_sub_edge)
- Packet_number_inFF <=Packet_number_inFF + 1'b1;
- else if (!Packet_number_add&&Packet_number_sub_edge)
- Packet_number_inFF <=Packet_number_inFF - 1'b1;
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Packet_number_inFF_reg <=0;
- else
- Packet_number_inFF_reg <=Packet_number_inFF;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Add_rd_reg_rdy_dl1 <=0;
- Add_rd_reg_rdy_dl2 <=0;
- end
- else
- begin
- Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy;
- Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1;
- end
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Add_rd_reg_dl1 <=0;
- else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2)
- Add_rd_reg_dl1 <=Add_rd_reg;
-
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Fifo_data_count <=0;
- else if (FullDuplex)
- Fifo_data_count
<=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
- else
- Fifo_data_count
<=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_reg_dl1[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
//for half duplex backoff requirement
-
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Fifo_ra_tmp <=0;
- else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark)
- Fifo_ra_tmp <=1;
- else
- Fifo_ra_tmp <=0;
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- begin
- Tx_Hwmark_pl <=0;
- Tx_Lwmark_pl <=0;
- end
- else
- begin
- Tx_Hwmark_pl <=Tx_Hwmark;
- Tx_Lwmark_pl <=Tx_Lwmark;
- end
-
-always @ (posedge Clk_SYS or posedge Reset)
- if (Reset)
- Tx_mac_wa <=0;
- else if (Fifo_data_count>=Tx_Hwmark_pl)
- Tx_mac_wa <=0;
- else if (Fifo_data_count<Tx_Lwmark_pl)
- Tx_mac_wa <=1;
-
-//******************************************************************************
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-//******************************************************************************
-//rd data to from FF .
-//domain Clk_MAC
-//******************************************************************************
-reg[35:0] Dout_dl1;
-reg Dout_reg_en /* synthesis syn_keep=1 */;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Dout_dl1 <=0;
- else
- Dout_dl1 <=Dout;
-
-always @ (Current_state_MAC or Next_state_MAC)
- if
((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
- Dout_reg_en =1;
- else
- Dout_reg_en =0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Dout_reg <=0;
- else if (Dout_reg_en)
- Dout_reg <=Dout_dl1;
-
-assign {Dout_eop,Dout_err,Dout_BE,Dout_data}=Dout_reg;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Current_state_MAC <=MAC_idle;
- else
- Current_state_MAC <=Next_state_MAC;
-
-always @ (Current_state_MAC or Fifo_rd or Dout_BE or Dout_eop or Fifo_rd_retry
- or Fifo_rd_finish or Empty or Fifo_rd or Fifo_eop)
- case (Current_state_MAC)
- MAC_idle:
- if (Empty&&Fifo_rd)
- Next_state_MAC=MAC_FF_Err;
- else if (Fifo_rd)
- Next_state_MAC=MAC_byte3;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_byte3:
- if (Fifo_rd_retry)
- Next_state_MAC=MAC_retry;
- else if (Fifo_eop)
- Next_state_MAC=MAC_wait_finish;
- else if (Fifo_rd&&!Fifo_eop)
- Next_state_MAC=MAC_byte2;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_byte2:
- if (Fifo_rd_retry)
- Next_state_MAC=MAC_retry;
- else if (Fifo_eop)
- Next_state_MAC=MAC_wait_finish;
- else if (Fifo_rd&&!Fifo_eop)
- Next_state_MAC=MAC_byte1;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_byte1:
- if (Fifo_rd_retry)
- Next_state_MAC=MAC_retry;
- else if (Fifo_eop)
- Next_state_MAC=MAC_wait_finish;
- else if (Fifo_rd&&!Fifo_eop)
- Next_state_MAC=MAC_byte0;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_byte0:
- if (Empty&&Fifo_rd&&!Fifo_eop)
- Next_state_MAC=MAC_FFEmpty;
- else if (Fifo_rd_retry)
- Next_state_MAC=MAC_retry;
- else if (Fifo_eop)
- Next_state_MAC=MAC_wait_finish;
- else if (Fifo_rd&&!Fifo_eop)
- Next_state_MAC=MAC_byte3;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_retry:
- Next_state_MAC=MAC_idle;
- MAC_wait_finish:
- if (Fifo_rd_finish)
- Next_state_MAC=MAC_pkt_sub;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_pkt_sub:
- Next_state_MAC=MAC_idle;
- MAC_FFEmpty:
- if (!Empty)
- Next_state_MAC=MAC_byte3;
- else
- Next_state_MAC=Current_state_MAC;
- MAC_FF_Err: //stopped state-machine need change
- Next_state_MAC=Current_state_MAC;
- default
- Next_state_MAC=MAC_idle;
- endcase
-//
-always @ (posedge Reset or posedge Clk_MAC)
- if (Reset)
- Add_rd_gray <=0;
- else
- begin
- Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
- end
-//
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_gray_dl1 <=0;
- else
- Add_wr_gray_dl1 <=Add_wr_gray;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_wr_ungray =0;
- else
- begin
- Add_wr_ungray[`MAC_RX_FF_DEPTH-1]
=Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
- for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
- Add_wr_ungray[i]
=Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
- end
-//empty
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Empty <=1;
- else if (Add_rd==Add_wr_ungray)
- Empty <=1;
- else
- Empty <=0;
-
-//ra
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_ra <=0;
- else
- Fifo_ra <=Fifo_ra_tmp;
-
-
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Pkt_sub_apply_tmp <=0;
- else if (Current_state_MAC==MAC_pkt_sub)
- Pkt_sub_apply_tmp <=1;
- else
- Pkt_sub_apply_tmp <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Pkt_sub_apply <=0;
- else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp)
- Pkt_sub_apply <=1;
- else
- Pkt_sub_apply <=0;
-
-//reg Add_rd for collison retry
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_reg <=0;
- else if (Fifo_rd_finish)
- Add_rd_reg <=Add_rd;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_reg_rdy_tmp <=0;
- else if (Fifo_rd_finish)
- Add_rd_reg_rdy_tmp <=1;
- else
- Add_rd_reg_rdy_tmp <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_reg_rdy <=0;
- else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp)
- Add_rd_reg_rdy <=1;
- else
- Add_rd_reg_rdy <=0;
-
-reg Add_rd_add /* synthesis syn_keep=1 */;
-
-always @ (Current_state_MAC or Next_state_MAC)
- if
((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
- Add_rd_add =1;
- else
- Add_rd_add =0;
-
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd <=0;
- else if (Current_state_MAC==MAC_retry)
- Add_rd <= Add_rd_reg;
- else if (Add_rd_add)
- Add_rd <= Add_rd + 1;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_jump_tmp <=0;
- else if (Current_state_MAC==MAC_retry)
- Add_rd_jump_tmp <=1;
- else
- Add_rd_jump_tmp <=0;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_jump_tmp_pl1 <=0;
- else
- Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Add_rd_jump <=0;
- else if (Current_state_MAC==MAC_retry)
- Add_rd_jump <=1;
- else if (Add_rd_jump_tmp_pl1)
- Add_rd_jump <=0;
-
-//gen Fifo_data
-
-
-always @ (Dout_data or Current_state_MAC)
- case (Current_state_MAC)
- MAC_byte3:
- Fifo_data =Dout_data[31:24];
- MAC_byte2:
- Fifo_data =Dout_data[23:16];
- MAC_byte1:
- Fifo_data =Dout_data[15:8];
- MAC_byte0:
- Fifo_data =Dout_data[7:0];
- default:
- Fifo_data =0;
- endcase
-//gen Fifo_da
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_rd_dl1 <=0;
- else
- Fifo_rd_dl1 <=Fifo_rd;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_da <=0;
- else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||
-
Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop)
- Fifo_da <=1;
- else
- Fifo_da <=0;
-
-//gen Fifo_data_err_empty
-assign Fifo_data_err_full=Dout_err;
-//gen Fifo_data_err_empty
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Current_state_MAC_reg <=0;
- else
- Current_state_MAC_reg <=Current_state_MAC;
-
-always @ (posedge Clk_MAC or posedge Reset)
- if (Reset)
- Fifo_data_err_empty <=0;
- else if (Current_state_MAC_reg==MAC_FFEmpty)
- Fifo_data_err_empty <=1;
- else
- Fifo_data_err_empty <=0;
-
-always @ (posedge Clk_MAC)
- if (Current_state_MAC_reg==MAC_FF_Err)
- begin
- $finish(2);
- $display("mac_tx_FF meet error status at time :%t",$time);
- end
-
-//gen Fifo_eop aligned to last valid data byte��
-always @ (Current_state_MAC or Dout_eop)
- if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00||
- Current_state_MAC==MAC_byte1&&Dout_BE==2'b11||
- Current_state_MAC==MAC_byte2&&Dout_BE==2'b10||
- Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop))
- Fifo_eop =1;
- else
- Fifo_eop =0;
-//******************************************************************************
-//******************************************************************************
-
-duram #(36,`MAC_TX_FF_DEPTH,"M4K") U_duram(
-.data_a (Din ),
-.wren_a (Wr_en ),
-.address_a (Add_wr ),
-.address_b (Add_rd ),
-.clock_a (Clk_SYS ),
-.clock_b (Clk_MAC ),
-.q_b (Dout ));
-
-endmodule
\ No newline at end of file
+ //gen Fifo_da
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_rd_dl1 <=0;
+ else
+ Fifo_rd_dl1 <=Fifo_rd;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_da <=0;
+ else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||
+
Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop)
+ Fifo_da <=1;
+ else
+ Fifo_da <=0;
+
+ //gen Fifo_data_err_empty
+ assign Fifo_data_err_full=Dout_err;
+ //gen Fifo_data_err_empty
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Current_state_MAC_reg <=0;
+ else
+ Current_state_MAC_reg <=Current_state_MAC;
+
+ always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Fifo_data_err_empty <=0;
+ else if (Current_state_MAC_reg==MAC_FFEmpty)
+ Fifo_data_err_empty <=1;
+ else
+ Fifo_data_err_empty <=0;
+
+ always @ (posedge Clk_MAC)
+ if (Current_state_MAC_reg==MAC_FF_Err)
+ begin
+ $finish(2);
+ $display("mac_tx_FF meet error status at time :%t",$time);
+ end
+
+ //gen Fifo_eop aligned to last valid data byte��
+ always @ (Current_state_MAC or Dout_eop)
+ if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00||
+ Current_state_MAC==MAC_byte1&&Dout_BE==2'b11||
+ Current_state_MAC==MAC_byte2&&Dout_BE==2'b10||
+ Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop))
+ Fifo_eop =1;
+ else
+ Fifo_eop =0;
+
//******************************************************************************
+ duram #(36,MAC_TX_FF_DEPTH)
+ U_duram(.data_a (Din ),
+ .wren_a (Wr_en ),
+ .address_a (Add_wr ),
+ .address_b (Add_rd ),
+ .clock_a (Clk_SYS ),
+ .clock_b (Clk_MAC ),
+ .q_b (Dout ));
+
+endmodule // MAC_tx_FF
Copied:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
(from rev 5191,
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v)
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -0,0 +1,646 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MAC_tx_ctrl.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
+//// ////
+//// Author(s): ////
+//// - Jon Gao (address@hidden) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: MAC_tx_Ctrl.v,v $
+// Revision 1.4 2006/06/25 04:58:56 maverickist
+// no message
+//
+// Revision 1.3 2006/01/19 14:07:54 maverickist
+// verification is complete.
+//
+// Revision 1.3 2005/12/16 06:44:17 Administrator
+// replaced tab with space.
+// passed 9.6k length frame test.
+//
+// Revision 1.2 2005/12/13 12:15:38 Administrator
+// no message
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+
+module MAC_tx_ctrl (
+Reset ,
+Clk ,
+//CRC_gen Interface
+CRC_init ,
+Frame_data ,
+Data_en ,
+CRC_rd ,
+CRC_end ,
+CRC_out ,
+//Ramdon_gen interfac
+Random_init ,
+RetryCnt ,
+Random_time_meet ,
+//flow control
+pause_apply ,
+pause_quanta_sub ,
+xoff_gen ,
+xoff_gen_complete ,
+xon_gen ,
+xon_gen_complete ,
+//MAC_tx_FF
+Fifo_data ,
+Fifo_rd ,
+Fifo_eop ,
+Fifo_da ,
+Fifo_rd_finish ,
+Fifo_rd_retry ,
+Fifo_ra ,
+Fifo_data_err_empty ,
+Fifo_data_err_full ,
+//RMII
+TxD ,
+TxEn ,
+CRS ,
+//MAC_tx_addr_add
+MAC_tx_addr_rd ,
+MAC_tx_addr_data ,
+MAC_tx_addr_init ,
+//RMON
+Tx_pkt_type_rmon ,
+Tx_pkt_length_rmon ,
+Tx_apply_rmon ,
+Tx_pkt_err_type_rmon,
+//CPU
+pause_frame_send_en ,
+pause_quanta_set ,
+MAC_tx_add_en ,
+FullDuplex ,
+MaxRetry ,
+IFGset
+);
+
+input Reset ;
+input Clk ;
+ //CRC_gen Interface
+output CRC_init ;
+output [7:0] Frame_data ;
+output Data_en ;
+output CRC_rd ;
+input CRC_end ;
+input [7:0] CRC_out ;
+ //Ramdon_gen interface
+output Random_init ;
+output [3:0] RetryCnt ;
+input Random_time_meet ;//levle hight indicate random time passed
away
+ //flow control
+input pause_apply ;
+output pause_quanta_sub ;
+input xoff_gen ;
+output xoff_gen_complete ;
+input xon_gen ;
+output xon_gen_complete ;
+ //MAC_rx_FF
+input [7:0] Fifo_data ;
+output Fifo_rd ;
+input Fifo_eop ;
+input Fifo_da ;
+output Fifo_rd_finish ;
+output Fifo_rd_retry ;
+input Fifo_ra ;
+input Fifo_data_err_empty ;
+input Fifo_data_err_full ;
+ //RMII
+output [7:0] TxD ;
+output TxEn ;
+input CRS ;
+ //MAC_tx_addr_add
+output MAC_tx_addr_init ;
+output MAC_tx_addr_rd ;
+input [7:0] MAC_tx_addr_data ;
+ //RMON
+output [2:0] Tx_pkt_type_rmon ;
+output [15:0] Tx_pkt_length_rmon ;
+output Tx_apply_rmon ;
+output [2:0] Tx_pkt_err_type_rmon;
+ //CPU
+input pause_frame_send_en ;
+input [15:0] pause_quanta_set ;
+input MAC_tx_add_en ;
+input FullDuplex ;
+input [3:0] MaxRetry ;
+input [5:0] IFGset ;
+//******************************************************************************
+//internal signals
+//******************************************************************************
+parameter StateIdle =4'd00;
+parameter StatePreamble =4'd01;
+parameter StateSFD =4'd02;
+parameter StateData =4'd03;
+parameter StatePause =4'd04;
+parameter StatePAD =4'd05;
+parameter StateFCS =4'd06;
+parameter StateIFG =4'd07;
+parameter StateJam =4'd08;
+parameter StateBackOff =4'd09;
+parameter StateJamDrop =4'd10;
+parameter StateFFEmptyDrop =4'd11;
+parameter StateSwitchNext =4'd12;
+parameter StateDefer =4'd13;
+parameter StateSendPauseFrame =4'd14;
+
+reg [3:0] Current_state /*synthesis syn_keep=1 */;
+reg [3:0] Next_state;
+reg [5:0] IFG_counter;
+reg [4:0] Preamble_counter;//
+reg [7:0] TxD_tmp ;
+reg TxEn_tmp ;
+reg [15:0] Tx_pkt_length_rmon ;
+reg Tx_apply_rmon ;
+reg Tx_apply_rmon_tmp ;
+reg Tx_apply_rmon_tmp_pl1;
+reg [2:0] Tx_pkt_err_type_rmon;
+reg [3:0] RetryCnt ;
+reg Random_init ;
+reg Fifo_rd_finish ;
+reg Fifo_rd_retry ;
+reg [7:0] TxD ;
+reg TxEn ;
+reg CRC_init ;
+reg Data_en ;
+reg CRC_rd ;
+reg Fifo_rd ;
+reg MAC_tx_addr_rd ;
+reg MAC_header_slot ;
+reg MAC_header_slot_tmp ;
+reg [2:0] Tx_pkt_type_rmon ;
+wire Collision ;
+reg MAC_tx_addr_init ;
+reg Src_MAC_ptr ;
+reg [7:0] IPLengthCounter ;//for pad append
+reg [1:0] PADCounter ;
+reg [7:0] JamCounter ;
+reg PktDrpEvenPtr ;
+reg [7:0] pause_counter ;
+reg pause_quanta_sub ;
+reg pause_frame_send_en_dl1 ;
+reg [15:0] pause_quanta_set_dl1 ;
+reg xoff_gen_complete ;
+reg xon_gen_complete ;
+//******************************************************************************
+//boundery signal processing
+//******************************************************************************
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ begin
+ pause_frame_send_en_dl1 <=0;
+ pause_quanta_set_dl1 <=0;
+ end
+ else
+ begin
+ pause_frame_send_en_dl1 <=pause_frame_send_en ;
+ pause_quanta_set_dl1 <=pause_quanta_set ;
+ end
+//******************************************************************************
+//state machine
+//******************************************************************************
+assign Collision=TxEn&CRS;
+
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ pause_counter <=0;
+ else if (Current_state!=StatePause)
+ pause_counter <=0;
+ else
+ pause_counter <=pause_counter+1;
+
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ IPLengthCounter <=0;
+ else if (Current_state==StateDefer)
+ IPLengthCounter <=0;
+ else if
(IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD))
+ IPLengthCounter <=IPLengthCounter+1;
+
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ PADCounter <=0;
+ else if (Current_state!=StatePAD)
+ PADCounter <=0;
+ else
+ PADCounter <=PADCounter+1;
+
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ Current_state <=StateDefer;
+ else
+ Current_state <=Next_state;
+
+always @ (*)
+ case (Current_state)
+ StateDefer:
+ if ((FullDuplex)||(!FullDuplex&&!CRS))
+ Next_state=StateIFG;
+ else
+ Next_state=Current_state;
+ StateIFG:
+ if (!FullDuplex&&CRS)
+ Next_state=StateDefer;
+ else if
((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove
some additional time
+ Next_state=StateIdle;
+ else
+ Next_state=Current_state;
+ StateIdle:
+ if (!FullDuplex&&CRS)
+ Next_state=StateDefer;
+ else if (pause_apply)
+ Next_state=StatePause;
+ else if
((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
+ Next_state=StatePreamble;
+ else
+ Next_state=Current_state;
+ StatePause:
+ if (pause_counter==512/8)
+ Next_state=StateDefer;
+ else
+ Next_state=Current_state;
+ StatePreamble:
+ if (!FullDuplex&&Collision)
+ Next_state=StateJam;
+ else if
((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6))
+ Next_state=StateSFD;
+ else
+ Next_state=Current_state;
+ StateSFD:
+ if (!FullDuplex&&Collision)
+ Next_state=StateJam;
+ else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
+ Next_state=StateSendPauseFrame;
+ else
+ Next_state=StateData;
+ StateSendPauseFrame:
+ if (IPLengthCounter==17)
+ Next_state=StatePAD;
+ else
+ Next_state=Current_state;
+ StateData:
+ if (!FullDuplex&&Collision)
+ Next_state=StateJam;
+ else if (Fifo_data_err_empty)
+ Next_state=StateFFEmptyDrop;
+ else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start
from 0
+ Next_state=StateFCS;
+ else if (Fifo_eop)
+ Next_state=StatePAD;
+ else
+ Next_state=StateData;
+ StatePAD:
+ if (!FullDuplex&&Collision)
+ Next_state=StateJam;
+ else if (IPLengthCounter>=59)
+ Next_state=StateFCS;
+ else
+ Next_state=Current_state;
+ StateJam:
+ if (RetryCnt<=MaxRetry&&JamCounter==16)
+ Next_state=StateBackOff;
+ else if (RetryCnt>MaxRetry)
+ Next_state=StateJamDrop;
+ else
+ Next_state=Current_state;
+ StateBackOff:
+ if (Random_time_meet)
+ Next_state =StateDefer;
+ else
+ Next_state =Current_state;
+ StateFCS:
+ if (!FullDuplex&&Collision)
+ Next_state =StateJam;
+ else if (CRC_end)
+ Next_state =StateSwitchNext;
+ else
+ Next_state =Current_state;
+ StateFFEmptyDrop:
+ if (Fifo_eop)
+ Next_state =StateSwitchNext;
+ else
+ Next_state =Current_state;
+ StateJamDrop:
+ if (Fifo_eop)
+ Next_state =StateSwitchNext;
+ else
+ Next_state =Current_state;
+ StateSwitchNext:
+ Next_state =StateDefer;
+ default:
+ Next_state =StateDefer;
+ endcase
+
+
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ JamCounter <=0;
+ else if (Current_state!=StateJam)
+ JamCounter <=0;
+ else if (Current_state==StateJam)
+ JamCounter <=JamCounter+1;
+
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ RetryCnt <=0;
+ else if (Current_state==StateSwitchNext)
+ RetryCnt <=0;
+ else if (Current_state==StateJam&&Next_state==StateBackOff)
+ RetryCnt <=RetryCnt + 1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ IFG_counter <=0;
+ else if (Current_state!=StateIFG)
+ IFG_counter <=0;
+ else
+ IFG_counter <=IFG_counter + 1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Preamble_counter <=0;
+ else if (Current_state!=StatePreamble)
+ Preamble_counter <=0;
+ else
+ Preamble_counter <=Preamble_counter+ 1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ PktDrpEvenPtr <=0;
+ else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
+ PktDrpEvenPtr <=~PktDrpEvenPtr;
+//******************************************************************************
+//generate output signals
+//******************************************************************************
+//CRC related
+always @(Current_state)
+ if (Current_state==StateSFD)
+ CRC_init =1;
+ else
+ CRC_init =0;
+
+assign Frame_data=TxD_tmp;
+
+always @(Current_state)
+ if
(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)
+ Data_en =1;
+ else
+ Data_en =0;
+
+always @(Current_state)
+ if (Current_state==StateFCS)
+ CRC_rd =1;
+ else
+ CRC_rd =0;
+
+//Ramdon_gen interface
+always @(Current_state or Next_state)
+ if (Current_state==StateJam&&Next_state==StateBackOff)
+ Random_init =1;
+ else
+ Random_init =0;
+
+//MAC_rx_FF
+//data have one cycle delay after fifo read signals
+always @ (*)
+ if (Current_state==StateData ||
+
Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) ||
+ Current_state==StateJamDrop&&PktDrpEvenPtr||
+ Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
+ Fifo_rd =1;
+ else
+ Fifo_rd =0;
+
+always @ (Current_state)
+ if (Current_state==StateSwitchNext)
+ Fifo_rd_finish =1;
+ else
+ Fifo_rd_finish =0;
+
+always @ (Current_state)
+ if (Current_state==StateJam)
+ Fifo_rd_retry =1;
+ else
+ Fifo_rd_retry =0;
+//RMII
+always @(Current_state)
+ if (Current_state==StatePreamble||Current_state==StateSFD||
+ Current_state==StateData||Current_state==StateSendPauseFrame||
+
Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
+ TxEn_tmp =1;
+ else
+ TxEn_tmp =0;
+
+//gen txd data
+always @(*)
+ case (Current_state)
+ StatePreamble:
+ TxD_tmp =8'h55;
+ StateSFD:
+ TxD_tmp =8'hd5;
+ StateData:
+ if (Src_MAC_ptr&&MAC_tx_add_en)
+ TxD_tmp =MAC_tx_addr_data;
+ else
+ TxD_tmp =Fifo_data;
+ StateSendPauseFrame:
+ if (Src_MAC_ptr&&MAC_tx_add_en)
+ TxD_tmp =MAC_tx_addr_data;
+ else
+ case (IPLengthCounter)
+ 7'd0: TxD_tmp =8'h01;
+ 7'd1: TxD_tmp =8'h80;
+ 7'd2: TxD_tmp =8'hc2;
+ 7'd3: TxD_tmp =8'h00;
+ 7'd4: TxD_tmp =8'h00;
+ 7'd5: TxD_tmp =8'h01;
+ 7'd12: TxD_tmp =8'h88;//type
+ 7'd13: TxD_tmp =8'h08;//
+ 7'd14: TxD_tmp =8'h00;//opcode
+ 7'd15: TxD_tmp =8'h01;
+ 7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];
+ 7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];
+// 7'd60: TxD_tmp =8'h26;
+// 7'd61: TxD_tmp =8'h6b;
+// 7'd62: TxD_tmp =8'hae;
+// 7'd63: TxD_tmp =8'h0a;
+ default:TxD_tmp =0;
+ endcase
+
+ StatePAD:
+ TxD_tmp =8'h00;
+ StateJam:
+ TxD_tmp =8'h01; //jam sequence
+ StateFCS:
+ TxD_tmp =CRC_out;
+ default:
+ TxD_tmp =2'b0;
+ endcase
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ begin
+ TxD <=0;
+ TxEn <=0;
+ end
+ else
+ begin
+ TxD <=TxD_tmp;
+ TxEn <=TxEn_tmp;
+ end
+//RMON
+
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_pkt_length_rmon <=0;
+ else if (Current_state==StateSFD)
+ Tx_pkt_length_rmon <=0;
+ else if
(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)
+ Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_apply_rmon_tmp <=0;
+ else if ((Fifo_eop&&Current_state==StateJamDrop)||
+ (Fifo_eop&&Current_state==StateFFEmptyDrop)||
+ CRC_end)
+ Tx_apply_rmon_tmp <=1;
+ else
+ Tx_apply_rmon_tmp <=0;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_apply_rmon_tmp_pl1 <=0;
+ else
+ Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_apply_rmon <=0;
+ else if ((Fifo_eop&&Current_state==StateJamDrop)||
+ (Fifo_eop&&Current_state==StateFFEmptyDrop)||
+ CRC_end)
+ Tx_apply_rmon <=1;
+ else if (Tx_apply_rmon_tmp_pl1)
+ Tx_apply_rmon <=0;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_pkt_err_type_rmon <=0;
+ else if(Fifo_eop&&Current_state==StateJamDrop)
+ Tx_pkt_err_type_rmon <=3'b001;//
+ else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
+ Tx_pkt_err_type_rmon <=3'b010;//underflow
+ else if(Fifo_eop&&Fifo_data_err_full)
+ Tx_pkt_err_type_rmon <=3'b011;//overflow
+ else if(CRC_end)
+ Tx_pkt_err_type_rmon <=3'b100;//normal
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ MAC_header_slot_tmp <=0;
+ else if(Current_state==StateSFD&&Next_state==StateData)
+ MAC_header_slot_tmp <=1;
+ else
+ MAC_header_slot_tmp <=0;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ MAC_header_slot <=0;
+ else
+ MAC_header_slot <=MAC_header_slot_tmp;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Tx_pkt_type_rmon <=0;
+ else if (Current_state==StateSendPauseFrame)
+ Tx_pkt_type_rmon <=3'b100;
+ else if(MAC_header_slot)
+ Tx_pkt_type_rmon <={1'b0,TxD[7:6]};
+
+
+always @(Tx_pkt_length_rmon)
+ if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
+ Src_MAC_ptr =1;
+ else
+ Src_MAC_ptr =0;
+
+//MAC_tx_addr_add
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ MAC_tx_addr_rd <=0;
+ else if
((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
+ MAC_tx_addr_rd <=1;
+ else
+ MAC_tx_addr_rd <=0;
+
+always @ (Tx_pkt_length_rmon or Fifo_rd)
+ if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
+ MAC_tx_addr_init=1;
+ else
+ MAC_tx_addr_init=0;
+
+//flow control
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ pause_quanta_sub <=0;
+ else if(pause_counter==512/8)
+ pause_quanta_sub <=1;
+ else
+ pause_quanta_sub <=0;
+
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ xoff_gen_complete <=0;
+ else if(Current_state==StateDefer&&xoff_gen)
+ xoff_gen_complete <=1;
+ else
+ xoff_gen_complete <=0;
+
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ xon_gen_complete <=0;
+ else if(Current_state==StateDefer&&xon_gen)
+ xon_gen_complete <=1;
+ else
+ xon_gen_complete <=0;
+
+endmodule
Deleted:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/Ramdon_gen.v
Copied:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v
(from rev 5191,
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/Ramdon_gen.v)
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// random_gen.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
+//// ////
+//// Author(s): ////
+//// - Jon Gao (address@hidden) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: Ramdon_gen.v,v $
+// Revision 1.3 2006/01/19 14:07:54 maverickist
+// verification is complete.
+//
+// Revision 1.2 2005/12/16 06:44:19 Administrator
+// replaced tab with space.
+// passed 9.6k length frame test.
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+
+module random_gen(
+Reset ,
+Clk ,
+Init ,
+RetryCnt ,
+Random_time_meet
+);
+input Reset ;
+input Clk ;
+input Init ;
+input [3:0] RetryCnt ;
+output Random_time_meet;
+
+//******************************************************************************
+//internal signals
+//******************************************************************************
+reg [9:0] Random_sequence ;
+reg [9:0] Random ;
+reg [9:0] Random_counter ;
+reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time
+reg Random_time_meet;
+
+//******************************************************************************
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Random_sequence <=0;
+ else
+ Random_sequence
<={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};
+
+always @ (RetryCnt or Random_sequence)
+ case (RetryCnt)
+ 4'h0 : Random={9'b0,Random_sequence[0]};
+ 4'h1 : Random={8'b0,Random_sequence[1:0]};
+ 4'h2 : Random={7'b0,Random_sequence[2:0]};
+ 4'h3 : Random={6'b0,Random_sequence[3:0]};
+ 4'h4 : Random={5'b0,Random_sequence[4:0]};
+ 4'h5 : Random={4'b0,Random_sequence[5:0]};
+ 4'h6 : Random={3'b0,Random_sequence[6:0]};
+ 4'h7 : Random={2'b0,Random_sequence[7:0]};
+ 4'h8 : Random={1'b0,Random_sequence[8:0]};
+ 4'h9 : Random={ Random_sequence[9:0]};
+ default : Random={ Random_sequence[9:0]};
+ endcase
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Slot_time_counter <=0;
+ else if(Init)
+ Slot_time_counter <=0;
+ else if(!Random_time_meet)
+ Slot_time_counter <=Slot_time_counter+1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Random_counter <=0;
+ else if (Init)
+ Random_counter <=Random;
+ else if (Random_counter!=0&&Slot_time_counter==255)
+ Random_counter <=Random_counter -1 ;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Random_time_meet <=1;
+ else if (Init)
+ Random_time_meet <=0;
+ else if (Random_counter==0)
+ Random_time_meet <=1;
+
+endmodule
+
+
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -140,7 +140,7 @@
.CRC_rd (CRC_rd ),
.CRC_end (CRC_end ),
.CRC_out (CRC_out ),
- //Ramdon_gen interfac (//Ramdon_gen interfac ),
+ //Random_gen interfac (//Random_gen interfac ),
.Random_init (Random_init ),
.RetryCnt (RetryCnt ),
.Random_time_meet (Random_time_meet ),
@@ -228,34 +228,34 @@
`else
assign MAC_tx_addr_data=0;
`endif
-MAC_tx_FF U_MAC_tx_FF(
-.Reset (Reset ),
-.Clk_MAC (Clk ),
-.Clk_SYS (Clk_user ),
- //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),
-.Fifo_data (Fifo_data ),
-.Fifo_rd (Fifo_rd ),
-.Fifo_rd_finish (Fifo_rd_finish ),
-.Fifo_rd_retry (Fifo_rd_retry ),
-.Fifo_eop (Fifo_eop ),
-.Fifo_da (Fifo_da ),
-.Fifo_ra (Fifo_ra ),
-.Fifo_data_err_empty (Fifo_data_err_empty ),
-.Fifo_data_err_full (Fifo_data_err_full ),
- //user interface (//user interface ),
-.Tx_mac_wa (Tx_mac_wa ),
-.Tx_mac_wr (Tx_mac_wr ),
-.Tx_mac_data (Tx_mac_data ),
-.Tx_mac_BE (Tx_mac_BE ),
-.Tx_mac_sop (Tx_mac_sop ),
-.Tx_mac_eop (Tx_mac_eop ),
- //host interface (//host interface ),
-.FullDuplex (FullDuplex ),
-.Tx_Hwmark (Tx_Hwmark ),
-.Tx_Lwmark (Tx_Lwmark )
-);
+MAC_tx_FF #(.MAC_TX_FF_DEPTH(9))
+ U_MAC_tx_FF(.Reset (Reset ),
+ .Clk_MAC (Clk ),
+ .Clk_SYS (Clk_user ),
+ //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),
+ .Fifo_data (Fifo_data ),
+ .Fifo_rd (Fifo_rd ),
+ .Fifo_rd_finish (Fifo_rd_finish ),
+ .Fifo_rd_retry (Fifo_rd_retry ),
+ .Fifo_eop (Fifo_eop ),
+ .Fifo_da (Fifo_da ),
+ .Fifo_ra (Fifo_ra ),
+ .Fifo_data_err_empty (Fifo_data_err_empty ),
+ .Fifo_data_err_full (Fifo_data_err_full ),
+ //user interface (//user interface ),
+ .Tx_mac_wa (Tx_mac_wa ),
+ .Tx_mac_wr (Tx_mac_wr ),
+ .Tx_mac_data (Tx_mac_data ),
+ .Tx_mac_BE (Tx_mac_BE ),
+ .Tx_mac_sop (Tx_mac_sop ),
+ .Tx_mac_eop (Tx_mac_eop ),
+ //host interface (//host interface ),
+ .FullDuplex (FullDuplex ),
+ .Tx_Hwmark (Tx_Hwmark ),
+ .Tx_Lwmark (Tx_Lwmark )
+ );
-Ramdon_gen U_Ramdon_gen(
+random_gen U_random_gen(
.Reset (Reset ),
.Clk (Clk ),
.Init (Random_init ),
@@ -263,4 +263,4 @@
.Random_time_meet (Random_time_meet )
);
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,6 +1,6 @@
//////////////////////////////////////////////////////////////////////
//// ////
-//// RMON_CTRL.v ////
+//// RMON_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
@@ -52,7 +52,7 @@
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
-module RMON_CTRL (
+module RMON_ctrl (
Clk ,
Reset ,
//RMON_CTRL
@@ -287,4 +287,4 @@
else if (Pipeline&&CurrentState==StateCPU)
CPU_rd_dout <=Douta;
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,46 +1,46 @@
-module RMON_dpram(
-Reset ,
-Clk ,
-//port-a for Rmon
-Addra,
-Dina,
-Douta,
-Wea,
-//port-b for CPU
-Addrb,
-Doutb
-);
+module RMON_dpram
+ (Reset ,
+ Clk ,
+ //port-a for Rmon
+ Addra,
+ Dina,
+ Douta,
+ Wea,
+ //port-b for CPU
+ Addrb,
+ Doutb
+ );
-input Reset ;
-input Clk ;
- //port-a for Rmon
-input [5:0] Addra;
-input [31:0] Dina;
-output [31:0] Douta;
-input Wea;
- //port-b for CPU
-input [5:0] Addrb;
-output [31:0] Doutb;
-//******************************************************************************
-//internal signals
-//******************************************************************************
+ input Reset ;
+ input Clk ;
+ //port-a for Rmon
+ input [5:0] Addra;
+ input [31:0] Dina;
+ output [31:0] Douta;
+ input Wea;
+ //port-b for CPU
+ input [5:0] Addrb;
+ output [31:0] Doutb;
+ //
******************************************************************************
+ //internal signals
+ //
******************************************************************************
-wire Clka;
-wire Clkb;
-assign Clka=Clk;
-assign #2 Clkb=Clk;
-//******************************************************************************
-
-duram #(32,6,"M4K") U_duram(
-.data_a (Dina ),
-.data_b (32'b0 ),
-.wren_a (Wea ),
-.wren_b (1'b0 ),
-.address_a (Addra ),
-.address_b (Addrb ),
-.clock_a (Clka ),
-.clock_b (Clkb ),
-.q_a (Douta ),
-.q_b (Doutb ));
-
-endmodule
\ No newline at end of file
+ wire Clka;
+ wire Clkb;
+ assign Clka=Clk;
+ assign #2 Clkb=Clk;
+ //
******************************************************************************
+
+ duram #(32,6)
+ U_duram(.data_a (Dina ),
+ .data_b (32'b0 ),
+ .wren_a (Wea ),
+ .wren_b (1'b0 ),
+ .address_a (Addra ),
+ .address_b (Addrb ),
+ .clock_a (Clka ),
+ .clock_b (Clkb ),
+ .q_a (Douta ),
+ .q_b (Doutb ));
+
+endmodule // RMON_dpram
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/RMON.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -53,131 +53,128 @@
// no message
//
-module RMON (
-Clk ,
-Reset ,
-//Tx_RMON
-Tx_pkt_type_rmon ,
-Tx_pkt_length_rmon ,
-Tx_apply_rmon ,
-Tx_pkt_err_type_rmon,
-//Tx_RMON
-Rx_pkt_type_rmon ,
-Rx_pkt_length_rmon ,
-Rx_apply_rmon ,
-Rx_pkt_err_type_rmon,
-//CPU
-CPU_rd_addr ,
-CPU_rd_apply ,
-CPU_rd_grant ,
-CPU_rd_dout
+module RMON
+ (Clk ,
+ Reset ,
+ //Tx_RMON
+ Tx_pkt_type_rmon ,
+ Tx_pkt_length_rmon ,
+ Tx_apply_rmon ,
+ Tx_pkt_err_type_rmon,
+ //Tx_RMON
+ Rx_pkt_type_rmon ,
+ Rx_pkt_length_rmon ,
+ Rx_apply_rmon ,
+ Rx_pkt_err_type_rmon,
+ //CPU
+ CPU_rd_addr ,
+ CPU_rd_apply ,
+ CPU_rd_grant ,
+ CPU_rd_dout
+ );
+
+ input Clk ;
+ input Reset ;
+ //Tx_RMON
+ input [2:0] Tx_pkt_type_rmon ;
+ input [15:0] Tx_pkt_length_rmon ;
+ input Tx_apply_rmon ;
+ input [2:0] Tx_pkt_err_type_rmon;
+ //Tx_RMON
+ input [2:0] Rx_pkt_type_rmon ;
+ input [15:0] Rx_pkt_length_rmon ;
+ input Rx_apply_rmon ;
+ input [2:0] Rx_pkt_err_type_rmon;
+ //CPU
+ input [5:0] CPU_rd_addr ;
+ input CPU_rd_apply ;
+ output CPU_rd_grant ;
+ output [31:0] CPU_rd_dout ;
+
+ //
******************************************************************************
+ //interface signals
+ //
******************************************************************************
+ wire Reg_apply_0 ;
+ wire [4:0] Reg_addr_0 ;
+ wire [15:0] Reg_data_0 ;
+ wire Reg_next_0 ;
+ wire Reg_apply_1 ;
+ wire [4:0] Reg_addr_1 ;
+ wire [15:0] Reg_data_1 ;
+ wire Reg_next_1 ;
+ wire [5:0] Addra ;
+ wire [31:0] Dina ;
+ wire [31:0] Douta ;
+ wire Wea ;
+
+ //
******************************************************************************
+
+ RMON_addr_gen
+ U_0_Rx_RMON_addr_gen(.Clk (Clk
),
+ .Reset (Reset ),
+ //RMON (//RMON ),
+ // .Pkt_type_rmon (Rx_pkt_type_rmon
),
+ .Pkt_length_rmon (Rx_pkt_length_rmon
),
+ .Apply_rmon (Rx_apply_rmon ),
+ .Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
+ //Rmon_ctrl (//Rmon_ctrl ),
+ .Reg_apply (Reg_apply_0 ),
+ .Reg_addr (Reg_addr_0 ),
+ .Reg_data (Reg_data_0
),
+ .Reg_next (Reg_next_0 ),
+ //CPU (//CPU
),
+ .Reg_drop_apply (
));
+
+ RMON_addr_gen
+ U_0_Tx_RMON_addr_gen(.Clk (Clk
),
+ .Reset (Reset
),
+ //RMON (//RMON ),
+ .Pkt_type_rmon (Tx_pkt_type_rmon
),
+ .Pkt_length_rmon (Tx_pkt_length_rmon
),
+ .Apply_rmon (Tx_apply_rmon ),
+ .Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
+ //Rmon_ctrl (//Rmon_ctrl ),
+ .Reg_apply (Reg_apply_1
),
+ .Reg_addr (Reg_addr_1
),
+ .Reg_data (Reg_data_1
),
+ .Reg_next (Reg_next_1
),
+ //CPU (//CPU
),
+ .Reg_drop_apply (
));
+
+ RMON_ctrl
+ U_RMON_ctrl(.Clk (Clk ),
+ .Reset (Reset ),
+ //RMON_CTRL (//RMON_CTRL ),
+ .Reg_apply_0 (Reg_apply_0 ),
+ .Reg_addr_0 (Reg_addr_0 ),
+ .Reg_data_0 (Reg_data_0 ),
+ .Reg_next_0 (Reg_next_0 ),
+ .Reg_apply_1 (Reg_apply_1 ),
+ .Reg_addr_1 (Reg_addr_1 ),
+ .Reg_data_1 (Reg_data_1 ),
+ .Reg_next_1 (Reg_next_1 ),
+ //dual-port ram (//dual-port ram ),
+ .Addra (Addra ),
+ .Dina (Dina ),
+ .Douta (Douta ),
+ .Wea (Wea ),
+ //CPU (//CPU ),
+ .CPU_rd_addr (CPU_rd_addr ),
+ .CPU_rd_apply (CPU_rd_apply ),
+ .CPU_rd_grant (CPU_rd_grant ),
+ .CPU_rd_dout (CPU_rd_dout )
+ );
-);
-input Clk ;
-input Reset ;
- //Tx_RMON
-input [2:0] Tx_pkt_type_rmon ;
-input [15:0] Tx_pkt_length_rmon ;
-input Tx_apply_rmon ;
-input [2:0] Tx_pkt_err_type_rmon;
- //Tx_RMON
-input [2:0] Rx_pkt_type_rmon ;
-input [15:0] Rx_pkt_length_rmon ;
-input Rx_apply_rmon ;
-input [2:0] Rx_pkt_err_type_rmon;
- //CPU
-input [5:0] CPU_rd_addr ;
-input CPU_rd_apply ;
-output CPU_rd_grant ;
-output [31:0] CPU_rd_dout ;
-
-//******************************************************************************
-//interface signals
-//******************************************************************************
-wire Reg_apply_0 ;
-wire [4:0] Reg_addr_0 ;
-wire [15:0] Reg_data_0 ;
-wire Reg_next_0 ;
-wire Reg_apply_1 ;
-wire [4:0] Reg_addr_1 ;
-wire [15:0] Reg_data_1 ;
-wire Reg_next_1 ;
-wire [5:0] Addra ;
-wire [31:0] Dina ;
-wire [31:0] Douta ;
-wire Wea ;
-
-//******************************************************************************
-
-assign RxAddrb=0;
-assign TxAddrb=0;
-
-RMON_addr_gen U_0_Rx_RMON_addr_gen(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON (//RMON ),
-.Pkt_type_rmon (Rx_pkt_type_rmon ),
-.Pkt_length_rmon (Rx_pkt_length_rmon ),
-.Apply_rmon (Rx_apply_rmon ),
-.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
- //Rmon_ctrl (//Rron_ctrl ),
-.Reg_apply (Reg_apply_0 ),
-.Reg_addr (Reg_addr_0 ),
-.Reg_data (Reg_data_0 ),
-.Reg_next (Reg_next_0 ),
- //CPU (//CPU ),
-.Reg_drop_apply ( ));
-
-RMON_addr_gen U_0_Tx_RMON_addr_gen(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON (//RMON ),
-.Pkt_type_rmon (Tx_pkt_type_rmon ),
-.Pkt_length_rmon (Tx_pkt_length_rmon ),
-.Apply_rmon (Tx_apply_rmon ),
-.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
- //Rmon_ctrl (//Rron_ctrl ),
-.Reg_apply (Reg_apply_1 ),
-.Reg_addr (Reg_addr_1 ),
-.Reg_data (Reg_data_1 ),
-.Reg_next (Reg_next_1 ),
- //CPU (//CPU ),
-.Reg_drop_apply ( ));
-
-RMON_CTRL U_RMON_CTRL(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON_CTRL (//RMON_CTRL ),
-.Reg_apply_0 (Reg_apply_0 ),
-.Reg_addr_0 (Reg_addr_0 ),
-.Reg_data_0 (Reg_data_0 ),
-.Reg_next_0 (Reg_next_0 ),
-.Reg_apply_1 (Reg_apply_1 ),
-.Reg_addr_1 (Reg_addr_1 ),
-.Reg_data_1 (Reg_data_1 ),
-.Reg_next_1 (Reg_next_1 ),
- //dual-port ram (//dual-port ram ),
-.Addra (Addra ),
-.Dina (Dina ),
-.Douta (Douta ),
-.Wea (Wea ),
- //CPU (//CPU ),
-.CPU_rd_addr (CPU_rd_addr ),
-.CPU_rd_apply (CPU_rd_apply ),
-.CPU_rd_grant (CPU_rd_grant ),
-.CPU_rd_dout (CPU_rd_dout )
-);
-
-RMON_dpram U_Rx_RMON_dpram(
-.Reset (Reset ),
-.Clk (Clk ),
-//port-a for Rmon (//port-a for Rmon ),
-.Addra (Addra ),
-.Dina (Dina ),
-.Douta ( ),
-.Wea (Wea ),
-//port-b for CPU (//port-b for CPU ),
-.Addrb (Addra ),
-.Doutb (Douta ));
-
-endmodule
\ No newline at end of file
+ RMON_dpram
+ U_Rx_RMON_dpram(.Reset (Reset ),
+ .Clk (Clk ),
+ //port-a for Rmon (//port-a for Rmon ),
+ .Addra (Addra ),
+ .Dina (Dina ),
+ .Douta ( ),
+ .Wea (Wea ),
+ //port-b for CPU (//port-b for CPU ),
+ .Addrb (Addra ),
+ .Doutb (Douta ));
+
+endmodule // RMON
Deleted:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_DIV2.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,5 +1,5 @@
-/CLK_DIV2.v/1.3/Thu Jan 19 14:07:56 2006//
/CLK_SWITCH.v/1.3/Thu Jan 19 14:07:56 2006//
-/duram.v/1.2/Thu Jan 19 14:07:56 2006//
D/altera////
D/xilinx////
+/duram.v/1.2/Wed May 2 02:54:45 2007//
+/CLK_DIV2.v/1.3/Wed May 2 06:49:15 2007//
Copied:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v
(from rev 5191,
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_DIV2.v)
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -0,0 +1,71 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// CLK_DIV2.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
+//// ////
+//// Author(s): ////
+//// - Jon Gao (address@hidden) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: CLK_DIV2.v,v $
+// Revision 1.3 2006/01/19 14:07:56 maverickist
+// verification is complete.
+//
+// Revision 1.2 2005/12/16 06:44:20 Administrator
+// replaced tab with space.
+// passed 9.6k length frame test.
+//
+// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
+// no message
+//
+
+
+//////////////////////////////////////////////////////////////////////
+// This file can only used for simulation .
+// You need to replace it with your own element according to technology
+//////////////////////////////////////////////////////////////////////
+
+module clkdiv2 (
+input Reset,
+input IN,
+output reg OUT
+);
+
+always @ (posedge IN or posedge Reset)
+ if (Reset)
+ OUT <=0;
+ else
+ OUT <=!OUT;
+
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,87 +1,103 @@
-module duram(
-data_a,
-data_b,
-wren_a,
-wren_b,
-address_a,
-address_b,
-clock_a,
-clock_b,
-q_a,
-q_b); //synthesis syn_black_box
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 5;
-parameter BLK_RAM_TYPE = "AUTO";
-parameter DURAM_MODE = "BIDIR_DUAL_PORT";
-parameter ADDR_DEPTH = 2**ADDR_WIDTH;
+module duram
+ (data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ address_a,
+ address_b,
+ clock_a,
+ clock_b,
+ q_a,
+ q_b);
+ parameter DATA_WIDTH = 32;
+ parameter ADDR_WIDTH = 5;
+ parameter ADDR_DEPTH = 1<<ADDR_WIDTH;
+
+ input [DATA_WIDTH-1:0] data_a;
+ input wren_a;
+ input [ADDR_WIDTH-1:0] address_a;
+ input clock_a;
+ output reg [DATA_WIDTH-1:0] q_a;
+
+ input [DATA_WIDTH-1:0] data_b;
+ input wren_b;
+ input [ADDR_WIDTH-1:0] address_b;
+ input clock_b;
+ output reg [DATA_WIDTH-1:0] q_b;
+
+ reg [DATA_WIDTH-1:0] ram [0:ADDR_DEPTH-1];
+
+ always @(posedge clock_a)
+ begin
+ if(wren_a)
+ ram[address_a] <= data_a;
+ q_a <= ram[address_a];
+ end
+
+ always @(posedge clock_b)
+ begin
+ if(wren_b)
+ ram[address_b] <= data_b;
+ q_b <= ram[address_b];
+ end
+
+endmodule // duram
-input [DATA_WIDTH -1:0] data_a;
-input wren_a;
-input [ADDR_WIDTH -1:0] address_a;
-input clock_a;
-output [DATA_WIDTH -1:0] q_a;
-input [DATA_WIDTH -1:0] data_b;
-input wren_b;
-input [ADDR_WIDTH -1:0] address_b;
-input clock_b;
-output [DATA_WIDTH -1:0] q_b;
+/*
+ altsyncram
+ U_altsyncram (.wren_a (wren_a),
+ .wren_b (wren_b),
+ .data_a (data_a),
+ .data_b (data_b),
+ .address_a (address_a),
+ .address_b (address_b),
+ .clock0 (clock_a),
+ .clock1 (clock_b),
+ .q_a (q_a),
+ .q_b (q_b),
+ // synopsys translate_off
+ .aclr0 (),
+ .aclr1 (),
+ .addressstall_a (),
+ .addressstall_b (),
+ .byteena_a (),
+ .byteena_b (),
+ .clocken0 (),
+ .clocken1 (),
+ .rden_b ()
+ // synopsys translate_on
+ );
-
+ //parameter BLK_RAM_TYPE = "AUTO";
+ //parameter DURAM_MODE = "BIDIR_DUAL_PORT";
+
+ defparam
+ U_altsyncram.intended_device_family = "Stratix",
+ U_altsyncram.ram_block_type = BLK_RAM_TYPE,
+ U_altsyncram.operation_mode = DURAM_MODE,
+ U_altsyncram.width_a = DATA_WIDTH,
+ U_altsyncram.widthad_a = ADDR_WIDTH,
+ U_altsyncram.width_b = DATA_WIDTH,
+ U_altsyncram.widthad_b = ADDR_WIDTH,
+ U_altsyncram.lpm_type = "altsyncram",
+ U_altsyncram.width_byteena_a = 1,
+ U_altsyncram.width_byteena_b = 1,
+ U_altsyncram.outdata_reg_a = "UNREGISTERED",
+ U_altsyncram.outdata_aclr_a = "NONE",
+ U_altsyncram.outdata_reg_b = "UNREGISTERED",
+ U_altsyncram.indata_aclr_a = "NONE",
+ U_altsyncram.wrcontrol_aclr_a = "NONE",
+ U_altsyncram.address_aclr_a = "NONE",
+ U_altsyncram.indata_reg_b = "CLOCK1",
+ U_altsyncram.address_reg_b = "CLOCK1",
+ U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1",
+ U_altsyncram.indata_aclr_b = "NONE",
+ U_altsyncram.wrcontrol_aclr_b = "NONE",
+ U_altsyncram.address_aclr_b = "NONE",
+ U_altsyncram.outdata_aclr_b = "NONE",
+ U_altsyncram.power_up_uninitialized = "FALSE";
-altsyncram U_altsyncram (
-.wren_a (wren_a),
-.wren_b (wren_b),
-.data_a (data_a),
-.data_b (data_b),
-.address_a (address_a),
-.address_b (address_b),
-.clock0 (clock_a),
-.clock1 (clock_b),
-.q_a (q_a),
-.q_b (q_b),
-// synopsys translate_off
-.aclr0 (),
-.aclr1 (),
-.addressstall_a (),
-.addressstall_b (),
-.byteena_a (),
-.byteena_b (),
-.clocken0 (),
-.clocken1 (),
-.rden_b ()
-// synopsys translate_on
-);
- defparam
- U_altsyncram.intended_device_family = "Stratix",
- U_altsyncram.ram_block_type = BLK_RAM_TYPE,
- U_altsyncram.operation_mode = DURAM_MODE,
- U_altsyncram.width_a = DATA_WIDTH,
- U_altsyncram.widthad_a = ADDR_WIDTH,
-// U_altsyncram.numwords_a = 256,
- U_altsyncram.width_b = DATA_WIDTH,
- U_altsyncram.widthad_b = ADDR_WIDTH,
-// U_altsyncram.numwords_b = 256,
- U_altsyncram.lpm_type = "altsyncram",
- U_altsyncram.width_byteena_a = 1,
- U_altsyncram.width_byteena_b = 1,
- U_altsyncram.outdata_reg_a = "UNREGISTERED",
- U_altsyncram.outdata_aclr_a = "NONE",
- U_altsyncram.outdata_reg_b = "UNREGISTERED",
- U_altsyncram.indata_aclr_a = "NONE",
- U_altsyncram.wrcontrol_aclr_a = "NONE",
- U_altsyncram.address_aclr_a = "NONE",
- U_altsyncram.indata_reg_b = "CLOCK1",
- U_altsyncram.address_reg_b = "CLOCK1",
- U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1",
- U_altsyncram.indata_aclr_b = "NONE",
- U_altsyncram.wrcontrol_aclr_b = "NONE",
- U_altsyncram.address_aclr_b = "NONE",
- U_altsyncram.outdata_aclr_b = "NONE",
- U_altsyncram.power_up_uninitialized = "FALSE";
-
-endmodule
-
-
+ */
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_clockgen.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_clockgen.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_clockgen.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -78,66 +78,65 @@
//
//
-`timescale 1ns/10ps
-
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
+
+ parameter Tp=1;
+
+ input Clk; // Input clock (Host clock)
+ input Reset; // Reset signal
+ input [7:0] Divider; // Divider (input clock will be divided by
the Divider[7:0])
+
+ output Mdc; // Output clock
+ output MdcEn; // Enable signal is asserted for one Clk
period before Mdc rises.
+ output MdcEn_n; // Enable signal is asserted for one Clk
period before Mdc falls.
+
+ reg Mdc;
+ reg [7:0] Counter;
+
+ wire CountEq0;
+ wire [7:0] CounterPreset;
+ wire [7:0] TempDivider;
+
+
+ assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; //
If smaller than 2
+ assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; //
We are counting half of period
+
+
+ // Counter counts half period
+ always @ (posedge Clk or posedge Reset)
+ begin
+ if(Reset)
+ Counter[7:0] <= #Tp 8'h1;
+ else
+ begin
+ if(CountEq0)
+ begin
+ Counter[7:0] <= #Tp CounterPreset[7:0];
+ end
+ else
+ Counter[7:0] <= #Tp Counter - 8'h1;
+ end
+ end
+
+
+ // Mdc is asserted every other half period
+ always @ (posedge Clk or posedge Reset)
+ begin
+ if(Reset)
+ Mdc <= #Tp 1'b0;
+ else
+ begin
+ if(CountEq0)
+ Mdc <= #Tp ~Mdc;
+ end
+ end
+
+
+ assign CountEq0 = Counter == 8'h0;
+ assign MdcEn = CountEq0 & ~Mdc;
+ assign MdcEn_n = CountEq0 & Mdc;
+
+endmodule // eth_clockgen
-parameter Tp=1;
-input Clk; // Input clock (Host clock)
-input Reset; // Reset signal
-input [7:0] Divider; // Divider (input clock will be divided by the
Divider[7:0])
-output Mdc; // Output clock
-output MdcEn; // Enable signal is asserted for one Clk period
before Mdc rises.
-output MdcEn_n; // Enable signal is asserted for one Clk period
before Mdc falls.
-
-reg Mdc;
-reg [7:0] Counter;
-
-wire CountEq0;
-wire [7:0] CounterPreset;
-wire [7:0] TempDivider;
-
-
-assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If
smaller than 2
-assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are
counting half of period
-
-
-// Counter counts half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Counter[7:0] <= #Tp 8'h1;
- else
- begin
- if(CountEq0)
- begin
- Counter[7:0] <= #Tp CounterPreset[7:0];
- end
- else
- Counter[7:0] <= #Tp Counter - 8'h1;
- end
-end
-
-
-// Mdc is asserted every other half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Mdc <= #Tp 1'b0;
- else
- begin
- if(CountEq0)
- Mdc <= #Tp ~Mdc;
- end
-end
-
-
-assign CountEq0 = Counter == 8'h0;
-assign MdcEn = CountEq0 & ~Mdc;
-assign MdcEn_n = CountEq0 & Mdc;
-
-endmodule
-
-
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v
2007-05-08 18:19:08 UTC (rev 5257)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v
2007-05-09 03:32:54 UTC (rev 5258)
@@ -1,4 +1,4 @@
-module Reg_int (
+module reg_int (
input Reset ,
input Clk_reg ,
input CSB ,
@@ -176,4 +176,4 @@
else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
RegOut <=CD_in_reg;
-endmodule
\ No newline at end of file
+endmodule
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- [Commit-gnuradio] r5258 - in gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode: bench/verilog rtl/verilog rtl/verilog/CVS rtl/verilog/MAC_rx rtl/verilog/MAC_tx rtl/verilog/MAC_tx/CVS rtl/verilog/RMON rtl/verilog/TECH rtl/verilog/TECH/CVS rtl/verilog/miim,
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