[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5256 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5256 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
|
Date: |
Tue, 8 May 2007 11:56:35 -0600 (MDT) |
Author: thottelt
Date: 2007-05-08 11:56:34 -0600 (Tue, 08 May 2007)
New Revision: 5256
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
Log:
underflow and internal overflow handling
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-08 01:20:56 UTC (rev 5255)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -1,7 +1,7 @@
module chan_fifo_reader
( reset, tx_clock, tx_strobe, adc_time, samples_format,
- fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
- overrun, underrun, tx_empty ) ;
+ fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+ underrun, tx_empty ) ;
parameter MAX_PAYLOAD = 504 ;
@@ -16,7 +16,6 @@
output reg skip ;
output reg [15:0] tx_q ;
output reg [15:0] tx_i ;
- output reg overrun ;
output reg underrun ;
output reg tx_empty ;
@@ -57,7 +56,6 @@
reader_next_state <= `IDLE;
rdreq <= 0;
skip <= 0;
- overrun <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-08 01:20:56 UTC (rev 5255)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -12,20 +12,20 @@
/* Some parameters for usage later on */
parameter DATA_WIDTH = 32 ;
- parameter FIFO_DEPTH = 128 ;
+ parameter PKT_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
- reg [DATA_WIDTH-1:0] usb_ram [FIFO_DEPTH*NUM_PACKETS-1:0] ;
+ reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
- reg [7:0] usb_ram_offset_out ;
+ reg [6:0] usb_ram_offset_out ;
reg [1:0] usb_ram_packet_out ;
- reg [7:0] usb_ram_offset_in ;
+ reg [6:0] usb_ram_offset_in ;
reg [1:0] usb_ram_packet_in ;
- wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
- wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
+ wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
+ wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
@@ -36,10 +36,12 @@
begin
if (reset)
pkt_waiting <= 0;
- else if (usb_ram_ain >= usb_ram_aout)
- pkt_waiting <= usb_ram_ain - usb_ram_aout >= FIFO_DEPTH;
+ else if (usb_ram_ain == usb_ram_aout)
+ pkt_waiting <= isfull ;
+ else if (usb_ram_ain > usb_ram_aout)
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= PKT_DEPTH;
else
- pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
FIFO_DEPTH;
+ pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >=
PKT_DEPTH;
end
// Check if there is room
@@ -50,9 +52,9 @@
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
- have_space <= (usb_ram_ain - usb_ram_aout) <= FIFO_DEPTH *
(NUM_PACKETS - 1);
+ have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH *
(NUM_PACKETS - 1))? 1 : 0;
else
- have_space <= (usb_ram_aout - usb_ram_ain) >= FIFO_DEPTH;
+ have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
/* RAM Write Address process */
@@ -66,20 +68,20 @@
else
if( pkt_complete )
begin
- usb_ram_packet_in <= usb_ram_packet_in + 1;
+ usb_ram_packet_in <= usb_ram_packet_in + 1;
+
usb_ram_offset_in <= 0;
+ if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
+ isfull <= 1 ;
end
else if( write_enable )
begin
if (usb_ram_offset_in == 7'b1111111)
begin
- usb_ram_offset_in <= 0;
- usb_ram_packet_in <= usb_ram_packet_in + 1;
+ usb_ram_offset_in <= 7'b1111111;
end
else
usb_ram_offset_in <= usb_ram_offset_in + 1 ;
- if (usb_ram_ain + 1 == usb_ram_aout)
- isfull <= 1;
end
end
@@ -106,18 +108,20 @@
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
+ isfull <= 0;
end
else if(read_enable) begin
if( usb_ram_offset_out == 7'b1111111 )
begin
+ isfull <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
end
- if (usb_ram_ain == usb_ram_aout)
- isfull <= 0;
+ /*if (usb_ram_ain + 1 == usb_ram_aout)
+ isfull <= 0; */
end
/* RAM Reading Process */
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-08 01:20:56 UTC (rev 5255)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -22,7 +22,7 @@
input wire clear_status ;
output wire have_space ;
- output reg tx_underrun ;
+ output wire tx_underrun ;
output wire tx_empty ;
output wire [15:0] tx_i_0 ;
output wire [15:0] tx_q_0 ;
@@ -47,7 +47,6 @@
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] overrun_chan ;
wire [NUM_CHAN:0] underrun_chan ;
wire [NUM_CHAN:0] txempty_chan ;
@@ -67,14 +66,17 @@
wire tdpf_pkt_waiting [NUM_CHAN:0] ;
wire tdpf_rdreq [NUM_CHAN:0] ;
wire tdpf_skip [NUM_CHAN:0] ;
- wire tdpf_have_space [NUM_CHAN:0] ;
+ wire [NUM_CHAN:0] tdpf_have_space ;
wire txstrobe_chan [NUM_CHAN:0] ;
assign have_space = ~tupf_wrfull ;
assign tupf_pkt_waiting = (tupf_usedw >= 128) ;
/* TODO: Figure out how to write this genericly */
- assign tx_empty = txempty_chan[0] | txempty_chan[1] ;
+ assign tx_empty = txempty_chan[0] & txempty_chan[1] ;
+ assign tx_underrun = underrun_chan[0] | underrun_chan[1] ;
+
+ /* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
@@ -109,7 +111,8 @@
.done_chan (done_chan),
.rdreq (tupf_rdreq),
.pkt_waiting (tupf_pkt_waiting),
- .fifodata (tupf_fifodata_out)
+ .fifodata (tupf_fifodata_out),
+ .have_space_chan (tdpf_have_space)
);
data_packet_fifo tx_data_packet_fifo_0
@@ -142,7 +145,6 @@
.samples_format (4'b0),
.tx_q (tx_q_0),
.tx_i (tx_i_0),
- .overrun (overrun_chan[0]),
.underrun (underrun_chan[0]),
.skip (tdpf_skip[0]),
.rdreq (tdpf_rdreq[0]),
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-05-08 01:20:56 UTC (rev 5255)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -1,5 +1,5 @@
module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
- rdreq, done_chan, WR_chan, tx_data_bus);
+ rdreq, done_chan, WR_chan, tx_data_bus, have_space_chan);
/* Module parameters */
parameter NUM_CHAN = 2 ;
@@ -8,12 +8,13 @@
input wire tx_clock ;
input wire reset ;
- input wire [WIDTH-1:0] fifodata ;
+ input wire [WIDTH-1:0] fifodata ;
input wire pkt_waiting ;
+ input wire [NUM_CHAN:0] have_space_chan ;
output reg rdreq ;
output reg [NUM_CHAN:0] done_chan ;
output reg [NUM_CHAN:0] WR_chan ;
- output reg [WIDTH-1:0] tx_data_bus ;
+ output reg [WIDTH-1:0] tx_data_bus ;
@@ -33,8 +34,8 @@
reg [2:0] reader_state ;
reg [2:0] reader_next_state ;
reg [4:0] channel ;
- reg [8:0] pkt_length ;
- reg [8:0] read_length ;
+ reg [9:0] pkt_length ;
+ reg [9:0] read_length ;
/* State Machine */
always @(posedge tx_clock)
@@ -63,25 +64,21 @@
`WAIT:
begin
reader_next_state <= `READ_HEADER ;
+ rdreq <= 0 ;
end
`READ_HEADER:
- begin
- reader_next_state <= `FORWARD_DATA ;
-
+ begin
/* Read header fields */
channel <= (fifodata & 32'h1F0000) ;
- pkt_length <= (fifodata & 16'h1FF) + 8 ;
- read_length <= 9'd4 ;
+ pkt_length <= (fifodata & 32'h1FF) + 8 ;
+ read_length <= 10'd0 ;
- /* Forward data */
- case (channel)
- `TXCHAN0: WR_chan[0] <= 1 ;
- `TXCHAN1: WR_chan[1] <= 1 ;
- `TXCMD: WR_chan[2] <= 1 ;
- default: WR_chan <= 1 ;
- endcase
- tx_data_bus <= fifodata ;
+ if (have_space_chan[channel])
+ begin
+ reader_next_state <= `FORWARD_DATA ;
+ rdreq <= 1;
+ end
end
`FORWARD_DATA:
@@ -104,6 +101,8 @@
default: done_chan[0] <= 1 ;
endcase
end
+ else
+ WR_chan[channel] <= 1 ;
if (read_length == PKT_SIZE - 8)
rdreq <= 0;
Modified:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-05-08 01:20:56 UTC (rev 5255)
+++ gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -36,14 +36,13 @@
//.debug(debug),
.tx_q(tx_q),
.tx_i(tx_i),
- .overrun(overrun),
.underrun(underrun),
.samples_format(4'd0),
.tx_strobe(tx_strobe) );
// Channel fifo
- data_packet_fifo tx_usb_fifo
+ data_packet_fifo tx_data_fifo
( .reset(reset),
.clock(txclock),
.ram_data_in(data_bus),
@@ -85,8 +84,7 @@
reset = 1'b0 ;
end
- // Write an entire packets worth of data
- // into the FIFO
+ //1
repeat (20) begin
@(posedge txclock)
WR = 1'b1 ;
@@ -109,6 +107,7 @@
i = 0;
pkt_complete <= 0;
+ //2
repeat (12) begin
@(posedge txclock)
WR = 1'b1 ;
@@ -131,10 +130,90 @@
WR <= 0;
i = 0;
pkt_complete <= 0;
- debug = 1;
@(posedge txclock)
WR = 1'b0 ;
+
+ //3
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ // Notify the fifo to increment the packet number
+ if (i == 11)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+
+ //4
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ // Notify the fifo to increment the packet number
+ if (i == 11)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+
+ //5
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ // Notify the fifo to increment the packet number
+ if (i == 11)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
end
always@(posedge adcclock) begin
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-08
01:20:56 UTC (rev 5255)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-05-08
17:56:34 UTC (rev 5256)
@@ -243,43 +243,41 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 18
+Project_Files_Count = 17
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ./usb_fifo_writer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = ./usb_packet_fifo2_test.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178390642 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178643008 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = ./fake_fx2_test.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = ./fake_fx2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178393232 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178478575 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178480013 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_10 = ./chan_fifo_readers_test.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178480129 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ./usb_packet_fifo_test.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_13 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = ./tx_buffer_test.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178480197 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397015 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_17 = ./usb_fifo_reader_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178480747 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178645334 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178634050 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178634500 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = ./chan_fifo_readers_test.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178644548 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232565 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = ./usb_packet_fifo_test.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = ./tx_buffer_test.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178645641 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178644305 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = ./usb_fifo_reader_test.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -309,6 +307,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/usb_packet_fifo_test.v 0
0} {Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-05-08 01:20:56 UTC (rev 5255)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-05-08 17:56:34 UTC (rev 5256)
@@ -1,5 +1,7 @@
module tx_buffer_inband_test();
+parameter TSTAMP = 16'hFFFF ;
+
// Inputs
reg usbclk;
reg bus_reset;
@@ -90,31 +92,99 @@
usbdata = 32;
// timestamp = now
else if (i == 2 || i == 3)
- usbdata = 16'hFFFF;
+ usbdata = TSTAMP;
else
usbdata = i ;
i = i + 1 ;
end
+ @(posedge usbclk)
+ WR = 1'b0 ;
i = 0;
- // Write one full packet (channel 1)
+ // Write one full packet (channel 0)
repeat (256) begin
@(posedge usbclk)
WR = 1'b1 ;
if (i == 0)
// channel
- usbdata = 1;
+ usbdata = 0;
else if (i == 1)
// payload size
usbdata = 504;
// timestamp = now
else if (i == 2 || i == 3)
- usbdata = 16'hFFFF;
+ usbdata = TSTAMP;
else
usbdata = i ;
i = i + 1 ;
end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ i = 0;
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+
+ i = 0;
+
+ // Write one full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usbdata = 0;
+ else if (i == 1)
+ // payload size
+ usbdata = 504;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ i = 0;
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
end
always
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5256 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations,
thottelt <=