[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

"Field" proposal for hex2

From: W. J. van der Laan
Subject: "Field" proposal for hex2
Date: Fri, 07 May 2021 15:14:38 +0000


I've been working on a better way to insert immediate values for RISC-V. 
Currently, every immediate value is a raw 32-bit word loaded from a PC-relative 
address, then jumped over. The same is done for jump and call addresses. 
Although it works, this has a high overhead. For example to load a value into 

    auipc t0, 0x0 ; load PC into t0
    lw t0, 12(t0) ; load t0 from offset 12 (value)
    j 8           ; jump over value
    0x12345678    ; value to load

On RISC-V the immediate fields are not byte-aligned, so inserting values at 
byte boundaries has limited use. So I've been working this syntax into 

    =(field)(target)         Absolute reference
    .(field)(target)         Relative (to current address) reference
    .(field)(target)<(base)  Relative reference with explicit base

For example:

    =U-4260 lui____%t6,0
    =I0x1234 addi___%t6,%t6,0
    =B8 beq____%s10,%s11,0
    .Jfdputc jal____0

The field value preceeds the instruction. A value can be specified directly as 
hex/decimal or as a label. `(field)` is one of RISC-V's instruction types in 
this case:

   byte 3   byte 2   byte 1   byte 0 (LE)
   31    24 23    16 15     8 7      0
   -------- -------- -------- --------
I  ba987654 3210.... ........ ........  ALU instructions with Immediate 
argument, and load
S  ba98765. ........ ....4321 0.......  Store
B  ca98765. ........ ....4321 b.......  conditional Branch
U  vutsrqpo nmlkjihg fedc.... ........  Upper, used for lui/auipc
J  ka987654 321bjihg fedc.... ........  unconditional Jump

(legend: 0..k is bit 0..20)

Abstractly, a field defines a pattern how a value is converted into a sequence 
of bytes to be XOR'ed into the next emitted bytes. This can be minimalistically 
implemented as a shift register, or ring buffer.

An implementation is here: https://github.com/laanwj/guix-mescc-tools (see the 
"hex2_linker, M1: RV fields, shift register" commit)

An version of mescc that uses it for RISCV code generation can be found here: 
https://github.com/laanwj/guix-mes (see the "mescc: Introduce fields and use 
them on RV64." commit and the ones after it)

If there is agreement that this is conceptually a way forward, we could specify 
a simple but flexible enough syntax to define field types in the .M2 file that 
is not RISC-V specific. The concept is flexible and allows for multiple fields 
per instruction, if so desired. Possibly it could replace some of the other 
hex2 special syntaxes.

In any case, using this throughout for RISC-V resulted in a 100% performance 
win. The generated code is still slow compared to gcc (even unoptimized) but it 
is a somewhat promising improvement :)


reply via email to

[Prev in Thread] Current Thread [Next in Thread]