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Porting mes to RISC-V 64 bit
From: |
W. J. van der Laan |
Subject: |
Porting mes to RISC-V 64 bit |
Date: |
Sun, 04 Apr 2021 20:05:20 +0000 |
Over the weekend I have been working on porting mes to RISC-V. I am aiming for
RV32IM and RV64IM e.g. `riscv32-unknown-linux-elf` and
`risc64-unknown-linux-elf`. But 64-bit is my primary aim at the moment because
it is a more common architecture for Linux RISC-V.
I got as far as having `mes-gcc` run on my SiFive Unleashed board, as well as
having the scaffold and mes tests pass for gcc (except forĀ 70-extern andĀ
80-setjmp which seem really impractical to handle for gcc). `mescc` also gets
to the help message but I haven't adapted it in any way for the architecture
yet.
The most work was adapting the syscall interface. RISC-V Linux uses
asm-generic's syscall list which has removed many of the legacy syscalls. I've
switched to using more modern replacements but only for RV64, other
architectures should be unaffected.
I expect that the biggest challenge in getting mescc to generate RISC-V
binaries is the assumption that there is a persistent flags register
(arch:a?->r and such). RISC-V instead has instructions that compare a register
against another register or zero and branch / set a value directly. So some
refactoring outside the architecture-specific module will be needed.
The latest state of my work can be found on the 'riscv64' branch here:
https://github.com/laanwj/guix-mes
A required patch to hex2_linker is on the 'riscv' branch here:
https://github.com/laanwj/guix-mescc-tools
How does the development process work? Should I send patches to this mailing
list for review when they are ready?
W.
- Porting mes to RISC-V 64 bit,
W. J. van der Laan <=