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Re: mes-tcc can build itself on arm, without long long or floats
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From: |
Jan Nieuwenhuizen |
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Subject: |
Re: mes-tcc can build itself on arm, without long long or floats |
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Date: |
Thu, 10 Dec 2020 23:13:28 +0100 |
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User-agent: |
Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) |
Danny Milosavljevic writes:
Hi Danny!
> On Wed, 09 Dec 2020 23:24:22 +0100
> Jan Nieuwenhuizen <janneke@gnu.org> wrote:
>
>> Finally I got an initial version of mes-tcc bootstrapped so that it can
>> build itself!
[..]
> That is awesome! \o/
Yes! \o/
>> The bad news is that when I try to enable either long longs of floats, a
>> corrupted bootX-tcc (boot2-tcc or boot3-tcc) is produced. The good news
>> is that when I do not enable those features, boot5-tcc fails only 12 of
>> 255 tests (as expected because we are missing some features).
>>
> If I can help in any way, please tell me.
Thanks for listening! So, I introduced HAVE_LONG_LONG_STUB as a
preliminary stage before introducing HAVE_LONG_LONG. This works and we
now also have long long!
> I could look at the assembly differences etc.
Yeah, differences are difficult...I don't have a baseline that I can
think of. We could try diffing with gcc-built versions, or with
versions without floats...dunno.
> It's interesting that it also happens with-only long longs. The floats
> I would have expected with the wrong FPU enabled, but long longs?
> Weird...
Yeah; I guess we were "just lucky" on x86. I guess it makes sense to
first make room in structs, on the stack etc. before starting to use
it for calculations; though I don't fully understand.
As for floats (the last big hurdle for tinycc now), I "discovered" that
besides floats, there are not only doubles but also long doubles. So,
we may want/need to introduce STUB stages or HAVE_LONG_DOULE...?
Another thing. I am now using TCC_ARM_VFP=1, but the default, gcc-built
version also uses TCC_CPU_VERSION=7 TCC_ARM_EABI=1 TCC_ARM_HARDFLOAT=1.
I briefly tried those, but that "seemed to give worse results". I
haven't really looked closely, though. Also, there's the code in
lib/armeabi.c, lib/libtcc1.c, and mes-source/lib/libtcc1.c to
consider...
Anyway, the boot3-tcc built with HAVE_FLOAT now gives the Bus error
below. Ideas?
Greetings,
Janneke
+ ./boot3-tcc -c -g -D TCC_TARGET_ARM=1 -D TCC_ARM_VFP=1 -o libtcc1.o
mes-source/gcc-lib/arm-mes/libtcc1.c
boot.sh: line 225: 23540 Bus error (core dumped)
./${program_prefix}tcc -c -g $CPP_TARGET_FLAG -o libtcc1.o $MES_LIB/libtcc1.c
[135]23:00:29 janneke@banana:~/src/tinycc [env]
$ gdb boot3-tcc
GNU gdb (Ubuntu 7.11.1-0ubuntu1~16.5) 7.11.1
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "arm-linux-gnueabihf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from boot3-tcc...done.
(gdb) r -c -g -D TCC_TARGET_ARM=1 -D TCC_ARM_VFP=1 -o libtcc1.o
mes-source/gcc-lib/arm-mes/libtcc1.c
Starting program: /home/janneke/src/tinycc/boot3-tcc -c -g -D TCC_TARGET_ARM=1
-D TCC_ARM_VFP=1 -o libtcc1.o mes-source/gcc-lib/arm-mes/libtcc1.c
Program received signal SIGBUS, Bus error.
init_putv () at tccgen.c:6301
6301 break;
(gdb) disassemble
Dump of assembler code for function init_putv:
0x000254fc <+0>: mov r12, sp
0x00025500 <+4>: push {r0, r1, r2}
0x00025504 <+8>: push {r11, r12, lr}
0x00025508 <+12>: mov r11, sp
0x0002550c <+16>: sub sp, r11, #104 ; 0x68
0x00025510 <+20>: ldr r0, [r11, #12]
0x00025514 <+24>: mov r2, #8
0x00025518 <+28>: mov r1, r0
0x0002551c <+32>: str r0, [r11, #-36] ; 0xffffffdc
0x00025520 <+36>: sub r0, r11, #32
0x00025524 <+40>: bl 0x438dc <__memmove>
0x00025528 <+44>: ldr r0, [r11, #-32] ; 0xffffffe0
0x0002552c <+48>: bic r0, r0, #2048 ; 0x800
0x00025530 <+52>: str r0, [r11, #-32] ; 0xffffffe0
0x00025534 <+56>: ldr r0, [r11, #16]
0x00025538 <+60>: cmp r0, #0
0x0002553c <+64>: beq 0x25d30 <init_putv+2100>
0x00025540 <+68>: sub r0, r11, #32
0x00025544 <+72>: bl 0x1be20 <gen_assign_cast>
0x00025548 <+76>: ldr r0, [r11, #12]
0x0002554c <+80>: ldr r1, [r0]
0x00025550 <+84>: and r1, r1, #15
0x00025554 <+88>: str r1, [r11, #-4]
0x00025558 <+92>: sub r1, r11, #44 ; 0x2c
0x0002555c <+96>: ldr r0, [r11, #12]
0x00025560 <+100>: bl 0x1b064 <type_size>
0x00025564 <+104>: str r0, [r11, #-40] ; 0xffffffd8
0x00025568 <+108>: ldr r0, [r11, #20]
0x0002556c <+112>: ldr r1, [r11, #-40] ; 0xffffffd8
0x00025570 <+116>: add r0, r0, r1
0x00025574 <+120>: mov r1, r0
0x00025578 <+124>: ldr r0, [r11, #16]
0x0002557c <+128>: bl 0x28ef4 <section_reserve>
0x00025580 <+132>: ldr r0, [r11, #16]
0x00025584 <+136>: add r0, r0, #4
0x00025588 <+140>: ldr r1, [r11, #20]
0x0002558c <+144>: ldr r2, [r0]
0x00025590 <+148>: add r1, r2, r1
0x00025594 <+152>: str r1, [r11, #-16]
0x00025598 <+156>: ldr r0, [r11, #12]
0x0002559c <+160>: ldr r1, [r0]
0x000255a0 <+164>: and r1, r1, #64 ; 0x40
0x000255a4 <+168>: cmp r1, #0
0x000255a8 <+172>: beq 0x255b0 <init_putv+180>
0x000255ac <+176>: b 0x255d4 <init_putv+216>
0x000255b0 <+180>: mov r0, #0
0x000255b4 <+184>: str r0, [r11, #-8]
0x000255b8 <+188>: mov r0, #32
0x000255bc <+192>: str r0, [r11, #-12]
0x000255c0 <+196>: mvn r0, #0
0x000255c4 <+200>: mvn r1, #0
0x000255c8 <+204>: str r0, [r11, #-24] ; 0xffffffe8
0x000255cc <+208>: str r1, [r11, #-20] ; 0xffffffec
0x000255d0 <+212>: b 0x25634 <init_putv+312>
0x000255d4 <+216>: ldr lr, [pc] ; 0x255dc <init_putv+224>
0x000255d8 <+220>: b 0x255e0 <init_putv+228>
0x000255dc <+224>: andeq r2, r6, r4, lsl #6
0x000255e0 <+228>: ldr r0, [lr]
0x000255e4 <+232>: ldr r1, [r0]
0x000255e8 <+236>: asr r1, r1, #19
0x000255ec <+240>: and r1, r1, #63 ; 0x3f
0x000255f0 <+244>: str r1, [r11, #-8]
0x000255f4 <+248>: ldr lr, [pc] ; 0x255fc <init_putv+256>
0x000255f8 <+252>: b 0x25600 <init_putv+260>
0x000255fc <+256>: andeq r2, r6, r4, lsl #6
0x00025600 <+260>: ldr r0, [lr]
0x00025604 <+264>: ldr r1, [r0]
0x00025608 <+268>: asr r1, r1, #25
0x0002560c <+272>: and r1, r1, #63 ; 0x3f
0x00025610 <+276>: str r1, [r11, #-12]
0x00025614 <+280>: ldr r2, [r11, #-12]
0x00025618 <+284>: mov r1, #0
0x0002561c <+288>: mov r0, #1
0x00025620 <+292>: bl 0x43038 <__ashldi3>
0x00025624 <+296>: subs r0, r0, #1
0x00025628 <+300>: sbc r1, r1, #0
0x0002562c <+304>: str r0, [r11, #-24] ; 0xffffffe8
0x00025630 <+308>: str r1, [r11, #-20] ; 0xffffffec
0x00025634 <+312>: ldr lr, [pc] ; 0x2563c <init_putv+320>
0x00025638 <+316>: b 0x25640 <init_putv+324>
0x0002563c <+320>: andeq r2, r6, r4, lsl #6
0x00025640 <+324>: ldr r0, [lr]
0x00025644 <+328>: add r0, r0, #8
0x00025648 <+332>: ldrh r1, [r0]
0x0002564c <+336>: and r1, r1, #560 ; 0x230
0x00025650 <+340>: cmp r1, #560 ; 0x230
0x00025654 <+344>: bne 0x25880 <init_putv+900>
0x00025658 <+348>: ldr lr, [pc] ; 0x25660 <init_putv+356>
0x0002565c <+352>: b 0x25664 <init_putv+360>
0x00025660 <+356>: andeq r2, r6, r4, lsl #6
0x00025664 <+360>: ldr r0, [lr]
0x00025668 <+364>: add r0, r0, #28
0x0002566c <+368>: ldr r1, [r0]
0x00025670 <+372>: ldr r0, [r1]
0x00025674 <+376>: cmp r0, #268435456 ; 0x10000000
0x00025678 <+380>: blt 0x25880 <init_putv+900>
0x0002567c <+384>: ldr lr, [pc] ; 0x25684 <init_putv+392>
0x00025680 <+388>: b 0x25688 <init_putv+396>
0x00025684 <+392>: andeq r2, r6, r4, lsl #6
0x00025688 <+396>: ldr r0, [lr]
0x0002568c <+400>: ldr r1, [r0]
0x00025690 <+404>: and r1, r1, #15
0x00025694 <+408>: cmp r1, #4
0x00025698 <+412>: beq 0x25880 <init_putv+900>
0x0002569c <+416>: ldr lr, [pc] ; 0x256a4 <init_putv+424>
0x000256a0 <+420>: b 0x256a8 <init_putv+428>
0x000256a4 <+424>: andeq r2, r6, r4, ror r3
0x000256a8 <+428>: ldr r0, [lr]
0x000256ac <+432>: add r0, r0, #4
0x000256b0 <+436>: ldr lr, [pc] ; 0x256b8 <init_putv+444>
0x000256b4 <+440>: b 0x256bc <init_putv+448>
0x000256b8 <+444>: andeq r2, r6, r4, lsl #6
0x000256bc <+448>: ldr r1, [lr]
0x000256c0 <+452>: add r1, r1, #28
0x000256c4 <+456>: ldr r2, [r1]
0x000256c8 <+460>: add r2, r2, #12
0x000256cc <+464>: ldr r1, [r2]
0x000256d0 <+468>: lsl r1, r1, #4
0x000256d4 <+472>: ldr r2, [r0]
0x000256d8 <+476>: add r1, r2, r1
0x000256dc <+480>: str r1, [r11, #-52] ; 0xffffffcc
0x000256e0 <+484>: ldr lr, [pc] ; 0x256e8 <init_putv+492>
0x000256e4 <+488>: b 0x256ec <init_putv+496>
0x000256e8 <+492>: ; <UNDEFINED> instruction: 0x000623b8
0x000256ec <+496>: ldr r0, [lr]
0x000256f0 <+500>: add r0, r0, #804 ; 0x324
0x000256f4 <+504>: ldr r1, [r11, #-52] ; 0xffffffcc
0x000256f8 <+508>: add r1, r1, #14
0x000256fc <+512>: ldrh r2, [r1]
0x00025700 <+516>: lsl r2, r2, #2
0x00025704 <+520>: ldr r1, [r0]
0x00025708 <+524>: add r1, r1, r2
0x0002570c <+528>: ldr r0, [r1]
0x00025710 <+532>: str r0, [r11, #-48] ; 0xffffffd0
0x00025714 <+536>: ldr r0, [r11, #-48] ; 0xffffffd0
0x00025718 <+540>: add r0, r0, #4
0x0002571c <+544>: ldr r1, [r11, #-52] ; 0xffffffcc
0x00025720 <+548>: add r1, r1, #4
0x00025724 <+552>: ldr r2, [r1]
0x00025728 <+556>: ldr r1, [r0]
0x0002572c <+560>: add r1, r1, r2
0x00025730 <+564>: ldr r2, [r11, #-40] ; 0xffffffd8
0x00025734 <+568>: ldr r0, [r11, #-16]
0x00025738 <+572>: bl 0x462cc <memmove>
0x0002573c <+576>: ldr r0, [r11, #-48] ; 0xffffffd0
0x00025740 <+580>: add r0, r0, #60 ; 0x3c
0x00025744 <+584>: ldr r1, [r0]
0x00025748 <+588>: cmp r1, #0
0x0002574c <+592>: beq 0x2587c <init_putv+896>
0x00025750 <+596>: ldr r0, [r11, #-48] ; 0xffffffd0
0x00025754 <+600>: add r0, r0, #60 ; 0x3c
0x00025758 <+604>: ldr r1, [r0]
0x0002575c <+608>: ldr r0, [r1]
0x00025760 <+612>: lsr r0, r0, #3
0x00025764 <+616>: str r0, [r11, #-60] ; 0xffffffc4
0x00025768 <+620>: ldr r0, [r11, #-48] ; 0xffffffd0
0x0002576c <+624>: add r0, r0, #60 ; 0x3c
0x00025770 <+628>: ldr r1, [r0]
0x00025774 <+632>: add r1, r1, #4
0x00025778 <+636>: ldr r0, [r11, #-48] ; 0xffffffd0
0x0002577c <+640>: add r0, r0, #60 ; 0x3c
0x00025780 <+644>: ldr r2, [r0]
0x00025784 <+648>: ldr r0, [r2]
0x00025788 <+652>: ldr r2, [r1]
0x0002578c <+656>: add r0, r2, r0
0x00025790 <+660>: str r0, [r11, #-56] ; 0xffffffc8
0x00025794 <+664>: ldr r0, [r11, #-60] ; 0xffffffc4
0x00025798 <+668>: mov r1, r0
0x0002579c <+672>: sub r0, r0, #1
0x000257a0 <+676>: str r0, [r11, #-60] ; 0xffffffc4
0x000257a4 <+680>: cmp r1, #0
0x000257a8 <+684>: beq 0x2587c <init_putv+896>
0x000257ac <+688>: ldr r0, [r11, #-56] ; 0xffffffc8
0x000257b0 <+692>: mov r1, r0
0x000257b4 <+696>: sub r0, r0, #8
0x000257b8 <+700>: str r0, [r11, #-56] ; 0xffffffc8
0x000257bc <+704>: ldr r0, [r11, #-56] ; 0xffffffc8
0x000257c0 <+708>: ldr r1, [r11, #-52] ; 0xffffffcc
0x000257c4 <+712>: add r1, r1, #4
0x000257c8 <+716>: ldr r2, [r1]
0x000257cc <+720>: ldr r1, [r11, #-40] ; 0xffffffd8
0x000257d0 <+724>: add r1, r2, r1
0x000257d4 <+728>: ldr r2, [r0]
0x000257d8 <+732>: cmp r2, r1
0x000257dc <+736>: bcc 0x257e4 <init_putv+744>
0x000257e0 <+740>: b 0x25794 <init_putv+664>
0x000257e4 <+744>: ldr r0, [r11, #-56] ; 0xffffffc8
0x000257e8 <+748>: ldr r1, [r11, #-52] ; 0xffffffcc
0x000257ec <+752>: add r1, r1, #4
0x000257f0 <+756>: ldr r2, [r0]
0x000257f4 <+760>: ldr r0, [r1]
0x000257f8 <+764>: cmp r2, r0
0x000257fc <+768>: bcs 0x25804 <init_putv+776>
0x00025800 <+772>: b 0x2587c <init_putv+896>
0x00025804 <+776>: ldr r0, [r11, #-56] ; 0xffffffc8
0x00025808 <+780>: ldr r1, [r11, #20]
0x0002580c <+784>: ldr r2, [r0]
0x00025810 <+788>: add r1, r1, r2
0x00025814 <+792>: ldr r0, [r11, #-52] ; 0xffffffcc
0x00025818 <+796>: add r0, r0, #4
0x0002581c <+800>: ldr r2, [r0]
0x00025820 <+804>: sub r1, r1, r2
0x00025824 <+808>: ldr r0, [r11, #-56] ; 0xffffffc8
0x00025828 <+812>: add r0, r0, #4
0x0002582c <+816>: ldr r2, [r0]
0x00025830 <+820>: and r2, r2, #255 ; 0xff
0x00025834 <+824>: ldr r0, [r11, #-56] ; 0xffffffc8
0x00025838 <+828>: add r0, r0, #4
0x0002583c <+832>: ldr r3, [r0]
0x00025840 <+836>: lsr r3, r3, #8
0x00025844 <+840>: mov r0, #0
0x00025848 <+844>: push {r0} ; (str r0, [sp, #-4]!)
0x0002584c <+848>: add sp, sp, #0
0x00025850 <+852>: push {r3} ; (str r3, [sp, #-4]!)
0x00025854 <+856>: mov r3, r2
0x00025858 <+860>: mov r2, r1
0x0002585c <+864>: ldr r1, [r11, #16]
0x00025860 <+868>: ldr lr, [pc] ; 0x25868 <init_putv+876>
0x00025864 <+872>: b 0x2586c <init_putv+880>
0x00025868 <+876>: andeq r2, r6, r4, ror r3
0x0002586c <+880>: ldr r0, [lr]
0x00025870 <+884>: bl 0x29b68 <put_elf_reloca>
0x00025874 <+888>: add sp, sp, #8
0x00025878 <+892>: b 0x25794 <init_putv+664>
0x0002587c <+896>: b 0x25d04 <init_putv+2056>
0x00025880 <+900>: ldr lr, [pc] ; 0x25888 <init_putv+908>
0x00025884 <+904>: b 0x2588c <init_putv+912>
0x00025888 <+908>: andeq r2, r6, r4, lsl #6
0x0002588c <+912>: ldr r0, [lr]
0x00025890 <+916>: add r0, r0, #8
0x00025894 <+920>: ldrh r1, [r0]
0x00025898 <+924>: and r1, r1, #512 ; 0x200
0x0002589c <+928>: cmp r1, #0
0x000258a0 <+932>: beq 0x25910 <init_putv+1044>
0x000258a4 <+936>: ldr r0, [r11, #-4]
0x000258a8 <+940>: cmp r0, #1
0x000258ac <+944>: beq 0x25900 <init_putv+1028>
0x000258b0 <+948>: ldr r0, [r11, #-4]
0x000258b4 <+952>: cmp r0, #2
0x000258b8 <+956>: beq 0x25900 <init_putv+1028>
0x000258bc <+960>: ldr r0, [r11, #-4]
0x000258c0 <+964>: cmp r0, #9
0x000258c4 <+968>: beq 0x25900 <init_putv+1028>
0x000258c8 <+972>: ldr r0, [r11, #-4]
0x000258cc <+976>: cmp r0, #10
0x000258d0 <+980>: beq 0x25900 <init_putv+1028>
0x000258d4 <+984>: ldr r0, [r11, #-4]
0x000258d8 <+988>: cmp r0, #12
0x000258dc <+992>: beq 0x25900 <init_putv+1028>
0x000258e0 <+996>: ldr r0, [r11, #-4]
0x000258e4 <+1000>: cmp r0, #0
0x000258e8 <+1004>: bne 0x258fc <init_putv+1024>
0x000258ec <+1008>: ldr r0, [r11, #-12]
0x000258f0 <+1012>: cmp r0, #32
0x000258f4 <+1016>: beq 0x258fc <init_putv+1024>
0x000258f8 <+1020>: b 0x25900 <init_putv+1028>
0x000258fc <+1024>: b 0x25910 <init_putv+1044>
0x00025900 <+1028>: ldr r0, [pc] ; 0x25908 <init_putv+1036>
0x00025904 <+1032>: b 0x2590c <init_putv+1040>
0x00025908 <+1036>: andeq sp, r4, r5, ror r1
0x0002590c <+1040>: bl 0x3ddb8 <tcc_error>
0x00025910 <+1044>: b 0x25cb0 <init_putv+1972>
0x00025914 <+1048>: ldr lr, [pc] ; 0x2591c <init_putv+1056>
0x00025918 <+1052>: b 0x25920 <init_putv+1060>
0x0002591c <+1056>: andeq r2, r6, r4, lsl #6
0x00025920 <+1060>: ldr r0, [lr]
0x00025924 <+1064>: add r0, r0, #12
0x00025928 <+1068>: ldr lr, [pc] ; 0x25930 <init_putv+1076>
0x0002592c <+1072>: b 0x25934 <init_putv+1080>
0x00025930 <+1076>: andeq r2, r6, r4, lsl #6
0x00025934 <+1080>: ldr r1, [lr]
0x00025938 <+1084>: add r1, r1, #12
0x0002593c <+1088>: ldr r2, [r1]
0x00025940 <+1092>: add r1, r1, #4
0x00025944 <+1096>: ldr r3, [r1]
0x00025948 <+1100>: cmp r3, #0
0x0002594c <+1104>: bne 0x25958 <init_putv+1116>
0x00025950 <+1108>: cmp r2, #0
0x00025954 <+1112>: beq 0x25960 <init_putv+1124>
0x00025958 <+1116>: mov r1, #1
0x0002595c <+1120>: b 0x25964 <init_putv+1128>
0x00025960 <+1124>: mov r1, #0
0x00025964 <+1128>: mov r2, r1
0x00025968 <+1132>: asr r2, r2, #31
0x0002596c <+1136>: str r1, [r0]
0x00025970 <+1140>: add r0, r0, #4
0x00025974 <+1144>: str r2, [r0]
0x00025978 <+1148>: ldr r0, [r11, #-16]
0x0002597c <+1152>: ldr lr, [pc] ; 0x25984 <init_putv+1160>
0x00025980 <+1156>: b 0x25988 <init_putv+1164>
0x00025984 <+1160>: andeq r2, r6, r4, lsl #6
0x00025988 <+1164>: ldr r1, [lr]
0x0002598c <+1168>: add r1, r1, #12
0x00025990 <+1172>: ldr r2, [r1]
0x00025994 <+1176>: add r1, r1, #4
0x00025998 <+1180>: ldr r3, [r1]
0x0002599c <+1184>: ldr r1, [r11, #-24] ; 0xffffffe8
0x000259a0 <+1188>: and r1, r2, r1
0x000259a4 <+1192>: ldr r2, [r11, #-20] ; 0xffffffec
0x000259a8 <+1196>: and r2, r3, r2
0x000259ac <+1200>: str r1, [r11, #-68] ; 0xffffffbc
0x000259b0 <+1204>: str r2, [r11, #-64] ; 0xffffffc0
0x000259b4 <+1208>: ldr r2, [r11, #-8]
0x000259b8 <+1212>: ldr r1, [r11, #-64] ; 0xffffffc0
0x000259bc <+1216>: str r0, [r11, #-72] ; 0xffffffb8
0x000259c0 <+1220>: ldr r0, [r11, #-68] ; 0xffffffbc
0x000259c4 <+1224>: bl 0x43038 <__ashldi3>
0x000259c8 <+1228>: ldr lr, [r11, #-72] ; 0xffffffb8
0x000259cc <+1232>: ldrb r2, [lr]
0x000259d0 <+1236>: mov r3, r2
0x000259d4 <+1240>: asr r3, r3, #31
0x000259d8 <+1244>: orr r0, r2, r0
0x000259dc <+1248>: orr r1, r3, r1
0x000259e0 <+1252>: and r0, r0, #255 ; 0xff
0x000259e4 <+1256>: mov r1, #0
0x000259e8 <+1260>: ldr r2, [r11, #-72] ; 0xffffffb8
0x000259ec <+1264>: strb r0, [r2]
0x000259f0 <+1268>: b 0x25d04 <init_putv+2056>
0x000259f4 <+1272>: ldr r0, [r11, #-16]
0x000259f8 <+1276>: ldr lr, [pc] ; 0x25a00 <init_putv+1284>
0x000259fc <+1280>: b 0x25a04 <init_putv+1288>
0x00025a00 <+1284>: andeq r2, r6, r4, lsl #6
0x00025a04 <+1288>: ldr r1, [lr]
0x00025a08 <+1292>: add r1, r1, #12
0x00025a0c <+1296>: ldr r2, [r1]
0x00025a10 <+1300>: add r1, r1, #4
0x00025a14 <+1304>: ldr r3, [r1]
0x00025a18 <+1308>: ldr r1, [r11, #-24] ; 0xffffffe8
0x00025a1c <+1312>: and r1, r2, r1
0x00025a20 <+1316>: ldr r2, [r11, #-20] ; 0xffffffec
0x00025a24 <+1320>: and r2, r3, r2
0x00025a28 <+1324>: str r1, [r11, #-80] ; 0xffffffb0
0x00025a2c <+1328>: str r2, [r11, #-76] ; 0xffffffb4
0x00025a30 <+1332>: ldr r2, [r11, #-8]
0x00025a34 <+1336>: ldr r1, [r11, #-76] ; 0xffffffb4
0x00025a38 <+1340>: str r0, [r11, #-84] ; 0xffffffac
0x00025a3c <+1344>: ldr r0, [r11, #-80] ; 0xffffffb0
0x00025a40 <+1348>: bl 0x43038 <__ashldi3>
0x00025a44 <+1352>: ldr lr, [r11, #-84] ; 0xffffffac
0x00025a48 <+1356>: ldrsh r2, [lr]
0x00025a4c <+1360>: mov r3, r2
0x00025a50 <+1364>: asr r3, r3, #31
0x00025a54 <+1368>: orr r0, r2, r0
0x00025a58 <+1372>: orr r1, r3, r1
0x00025a5c <+1376>: lsl r0, r0, #16
0x00025a60 <+1380>: mov r1, #0
0x00025a64 <+1384>: asr r0, r0, #16
0x00025a68 <+1388>: mov r1, r0
0x00025a6c <+1392>: asr r1, r1, #31
0x00025a70 <+1396>: ldr r2, [r11, #-84] ; 0xffffffac
0x00025a74 <+1400>: strh r0, [r2]
0x00025a78 <+1404>: b 0x25d04 <init_putv+2056>
0x00025a7c <+1408>: ldr r0, [r11, #-16]
0x00025a80 <+1412>: ldr lr, [pc] ; 0x25a88 <init_putv+1420>
0x00025a84 <+1416>: b 0x25a8c <init_putv+1424>
0x00025a88 <+1420>: andeq r2, r6, r4, lsl #6
0x00025a8c <+1424>: ldr r1, [lr]
0x00025a90 <+1428>: add r1, r1, #12
0x00025a94 <+1432>: vldr s0, [r1]
0x00025a98 <+1436>: vstr s0, [r0]
0x00025a9c <+1440>: b 0x25d04 <init_putv+2056>
0x00025aa0 <+1444>: ldr r0, [r11, #-16]
0x00025aa4 <+1448>: ldr lr, [pc] ; 0x25aac <init_putv+1456>
0x00025aa8 <+1452>: b 0x25ab0 <init_putv+1460>
0x00025aac <+1456>: andeq r2, r6, r4, lsl #6
0x00025ab0 <+1460>: ldr r1, [lr]
0x00025ab4 <+1464>: add r1, r1, #12
0x00025ab8 <+1468>: vldr d0, [r1]
0x00025abc <+1472>: vstr d0, [r0]
=> 0x00025ac0 <+1476>: b 0x25d04 <init_putv+2056>
0x00025ac4 <+1480>: ldr r0, [r11, #-16]
0x00025ac8 <+1484>: ldr lr, [pc] ; 0x25ad0 <init_putv+1492>
0x00025acc <+1488>: b 0x25ad4 <init_putv+1496>
0x00025ad0 <+1492>: andeq r2, r6, r4, lsl #6
0x00025ad4 <+1496>: ldr r1, [lr]
0x00025ad8 <+1500>: add r1, r1, #12
0x00025adc <+1504>: vldr d0, [r1]
0x00025ae0 <+1508>: vstr d0, [r0]
0x00025ae4 <+1512>: nop ; (mov r0, r0)
0x00025ae8 <+1516>: b 0x25d04 <init_putv+2056>
0x00025aec <+1520>: ldr r0, [r11, #-16]
0x00025af0 <+1524>: ldr lr, [pc] ; 0x25af8 <init_putv+1532>
0x00025af4 <+1528>: b 0x25afc <init_putv+1536>
0x00025af8 <+1532>: andeq r2, r6, r4, lsl #6
0x00025afc <+1536>: ldr r1, [lr]
0x00025b00 <+1540>: add r1, r1, #12
0x00025b04 <+1544>: ldr r2, [r1]
0x00025b08 <+1548>: add r1, r1, #4
0x00025b0c <+1552>: ldr r3, [r1]
0x00025b10 <+1556>: ldr r1, [r11, #-24] ; 0xffffffe8
0x00025b14 <+1560>: and r1, r2, r1
0x00025b18 <+1564>: ldr r2, [r11, #-20] ; 0xffffffec
0x00025b1c <+1568>: and r2, r3, r2
0x00025b20 <+1572>: str r1, [r11, #-92] ; 0xffffffa4
0x00025b24 <+1576>: str r2, [r11, #-88] ; 0xffffffa8
0x00025b28 <+1580>: ldr r2, [r11, #-8]
0x00025b2c <+1584>: ldr r1, [r11, #-88] ; 0xffffffa8
0x00025b30 <+1588>: str r0, [r11, #-96] ; 0xffffffa0
0x00025b34 <+1592>: ldr r0, [r11, #-92] ; 0xffffffa4
0x00025b38 <+1596>: bl 0x43038 <__ashldi3>
0x00025b3c <+1600>: ldr lr, [r11, #-96] ; 0xffffffa0
0x00025b40 <+1604>: ldr r2, [lr]
0x00025b44 <+1608>: ldr r3, [r11, #-96] ; 0xffffffa0
0x00025b48 <+1612>: add r3, r3, #4
0x00025b4c <+1616>: ldr r12, [r3]
0x00025b50 <+1620>: orr r0, r2, r0
0x00025b54 <+1624>: orr r1, r12, r1
0x00025b58 <+1628>: ldr r2, [r11, #-96] ; 0xffffffa0
0x00025b5c <+1632>: str r0, [r2]
0x00025b60 <+1636>: add r2, r2, #4
0x00025b64 <+1640>: str r1, [r2]
0x00025b68 <+1644>: b 0x25d04 <init_putv+2056>
0x00025b6c <+1648>: ldr lr, [pc] ; 0x25b74 <init_putv+1656>
0x00025b70 <+1652>: b 0x25b78 <init_putv+1660>
0x00025b74 <+1656>: andeq r2, r6, r4, lsl #6
0x00025b78 <+1660>: ldr r0, [lr]
0x00025b7c <+1664>: add r0, r0, #12
0x00025b80 <+1668>: ldr r1, [r0]
0x00025b84 <+1672>: add r0, r0, #4
0x00025b88 <+1676>: ldr r2, [r0]
0x00025b8c <+1680>: ldr r0, [r11, #-24] ; 0xffffffe8
0x00025b90 <+1684>: and r0, r1, r0
0x00025b94 <+1688>: ldr r1, [r11, #-20] ; 0xffffffec
0x00025b98 <+1692>: and r1, r2, r1
0x00025b9c <+1696>: ldr r2, [r11, #-8]
0x00025ba0 <+1700>: bl 0x43038 <__ashldi3>
0x00025ba4 <+1704>: str r0, [r11, #-100] ; 0xffffff9c
0x00025ba8 <+1708>: ldr lr, [pc] ; 0x25bb0 <init_putv+1716>
0x00025bac <+1712>: b 0x25bb4 <init_putv+1720>
0x00025bb0 <+1716>: andeq r2, r6, r4, lsl #6
0x00025bb4 <+1720>: ldr r0, [lr]
0x00025bb8 <+1724>: add r0, r0, #8
0x00025bbc <+1728>: ldrh r1, [r0]
0x00025bc0 <+1732>: and r1, r1, #512 ; 0x200
0x00025bc4 <+1736>: cmp r1, #0
0x00025bc8 <+1740>: beq 0x25bf4 <init_putv+1784>
0x00025bcc <+1744>: ldr lr, [pc] ; 0x25bd4 <init_putv+1752>
0x00025bd0 <+1748>: b 0x25bd8 <init_putv+1756>
0x00025bd4 <+1752>: andeq r2, r6, r4, lsl #6
0x00025bd8 <+1756>: ldr r0, [lr]
0x00025bdc <+1760>: add r0, r0, #28
0x00025be0 <+1764>: mov r3, #2
0x00025be4 <+1768>: ldr r2, [r11, #20]
0x00025be8 <+1772>: ldr r1, [r0]
0x00025bec <+1776>: ldr r0, [r11, #16]
0x00025bf0 <+1780>: bl 0x14dd4 <greloc>
0x00025bf4 <+1784>: ldr r0, [r11, #-16]
0x00025bf8 <+1788>: ldr r1, [r0]
0x00025bfc <+1792>: ldr r2, [r11, #-100] ; 0xffffff9c
0x00025c00 <+1796>: orr r1, r1, r2
0x00025c04 <+1800>: str r1, [r0]
0x00025c08 <+1804>: b 0x25d04 <init_putv+2056>
0x00025c0c <+1808>: ldr lr, [pc] ; 0x25c14 <init_putv+1816>
0x00025c10 <+1812>: b 0x25c18 <init_putv+1820>
0x00025c14 <+1816>: andeq r2, r6, r4, lsl #6
0x00025c18 <+1820>: ldr r0, [lr]
0x00025c1c <+1824>: add r0, r0, #12
0x00025c20 <+1828>: ldr r1, [r0]
0x00025c24 <+1832>: add r0, r0, #4
0x00025c28 <+1836>: ldr r2, [r0]
0x00025c2c <+1840>: ldr r0, [r11, #-24] ; 0xffffffe8
0x00025c30 <+1844>: and r0, r1, r0
0x00025c34 <+1848>: ldr r1, [r11, #-20] ; 0xffffffec
0x00025c38 <+1852>: and r1, r2, r1
0x00025c3c <+1856>: ldr r2, [r11, #-8]
0x00025c40 <+1860>: bl 0x43038 <__ashldi3>
0x00025c44 <+1864>: str r0, [r11, #-104] ; 0xffffff98
0x00025c48 <+1868>: ldr lr, [pc] ; 0x25c50 <init_putv+1876>
0x00025c4c <+1872>: b 0x25c54 <init_putv+1880>
0x00025c50 <+1876>: andeq r2, r6, r4, lsl #6
0x00025c54 <+1880>: ldr r0, [lr]
0x00025c58 <+1884>: add r0, r0, #8
0x00025c5c <+1888>: ldrh r1, [r0]
0x00025c60 <+1892>: and r1, r1, #512 ; 0x200
0x00025c64 <+1896>: cmp r1, #0
0x00025c68 <+1900>: beq 0x25c94 <init_putv+1944>
0x00025c6c <+1904>: ldr lr, [pc] ; 0x25c74 <init_putv+1912>
0x00025c70 <+1908>: b 0x25c78 <init_putv+1916>
0x00025c74 <+1912>: andeq r2, r6, r4, lsl #6
0x00025c78 <+1916>: ldr r0, [lr]
0x00025c7c <+1920>: add r0, r0, #28
0x00025c80 <+1924>: mov r3, #2
0x00025c84 <+1928>: ldr r2, [r11, #20]
0x00025c88 <+1932>: ldr r1, [r0]
0x00025c8c <+1936>: ldr r0, [r11, #16]
0x00025c90 <+1940>: bl 0x14dd4 <greloc>
0x00025c94 <+1944>: ldr r0, [r11, #-16]
0x00025c98 <+1948>: ldr r1, [r0]
0x00025c9c <+1952>: ldr r2, [r11, #-104] ; 0xffffff98
0x00025ca0 <+1956>: orr r1, r1, r2
0x00025ca4 <+1960>: str r1, [r0]
0x00025ca8 <+1964>: b 0x25d04 <init_putv+2056>
0x00025cac <+1968>: b 0x25d04 <init_putv+2056>
0x00025cb0 <+1972>: ldr r0, [r11, #-4]
0x00025cb4 <+1976>: cmp r0, #9
0x00025cb8 <+1980>: bgt 0x25ce8 <init_putv+2028>
0x00025cbc <+1984>: cmp r0, #9
0x00025cc0 <+1988>: bge 0x25aa0 <init_putv+1444>
0x00025cc4 <+1992>: cmp r0, #1
0x00025cc8 <+1996>: beq 0x25978 <init_putv+1148>
0x00025ccc <+2000>: cmp r0, #2
0x00025cd0 <+2004>: beq 0x259f4 <init_putv+1272>
0x00025cd4 <+2008>: cmp r0, #4
0x00025cd8 <+2012>: beq 0x25b6c <init_putv+1648>
0x00025cdc <+2016>: cmp r0, #8
0x00025ce0 <+2020>: beq 0x25a7c <init_putv+1408>
0x00025ce4 <+2024>: b 0x25c0c <init_putv+1808>
0x00025ce8 <+2028>: cmp r0, #10
0x00025cec <+2032>: beq 0x25ac4 <init_putv+1480>
0x00025cf0 <+2036>: cmp r0, #11
0x00025cf4 <+2040>: beq 0x25914 <init_putv+1048>
0x00025cf8 <+2044>: cmp r0, #12
0x00025cfc <+2048>: beq 0x25aec <init_putv+1520>
0x00025d00 <+2052>: b 0x25c0c <init_putv+1808>
0x00025d04 <+2056>: ldr lr, [pc] ; 0x25d0c <init_putv+2064>
0x00025d08 <+2060>: b 0x25d10 <init_putv+2068>
0x00025d0c <+2064>: andeq r2, r6, r4, lsl #6
0x00025d10 <+2068>: ldr r0, [lr]
0x00025d14 <+2072>: mov r1, r0
0x00025d18 <+2076>: sub r0, r0, #32
0x00025d1c <+2080>: ldr lr, [pc] ; 0x25d24 <init_putv+2088>
0x00025d20 <+2084>: b 0x25d28 <init_putv+2092>
0x00025d24 <+2088>: andeq r2, r6, r4, lsl #6
0x00025d28 <+2092>: str r0, [lr]
0x00025d2c <+2096>: b 0x25d54 <init_putv+2136>
0x00025d30 <+2100>: ldr r2, [r11, #20]
0x00025d34 <+2104>: ldr r1, [pc] ; 0x25d3c <init_putv+2112>
0x00025d38 <+2108>: b 0x25d40 <init_putv+2116>
0x00025d3c <+2112>: andeq r0, r0, r2, lsr r1
0x00025d40 <+2116>: sub r0, r11, #32
0x00025d44 <+2120>: bl 0x15978 <vset>
0x00025d48 <+2124>: bl 0x156ac <vswap>
0x00025d4c <+2128>: bl 0x1c230 <vstore>
0x00025d50 <+2132>: bl 0x157bc <vpop>
0x00025d54 <+2136>: ldm r11, {r11, sp, pc}
End of assembler dump.
--
Jan Nieuwenhuizen <janneke@gnu.org> | GNU LilyPond http://lilypond.org
Freelance IT http://JoyofSource.com | Avatar® http://AvatarAcademy.com