[bug-mes] ARM instruction encoding of "halfword data transfer with immediate offset" is difficult in M1

[Danny Milosavljevic]

Hi,

just a heads-up, there's a strange encoding of some ARM instruction that I 
don't know how to represent in M1.

It's Halfword data transfer with immediate offset, for example:

  STRH %r0, [%fp, +#2]

The immediate offset is split into two parts and the parts encoded in 
non-consecutive bit blocks.

I can work around it using a scratch register, but just so we don't forget it I 
write this.

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