Re: [bug-mes] mescc and Load/Store architectures

[Danny Milosavljevic]

Hi Jeremiah,

On Fri, 08 Feb 2019 02:29:01 +0000
address@hidden wrote:

> If you are willing to be responsible for the ARM port, you can do
> anything you want to the ARM specific rules.

Sure.

> %label was correct with the Architectural displacement but !label didn't
> agree with that calculation and I saw no issue with different sized
> relative pointers having different calculations.

Yes, but does that imply that there a user for ARM displacements already?
(the one using the %label and !label)

I don't want to break it, but I can't think of any place where ARM would
have 8 bit offsets in branches.  What are displacements used for?  Branches
and what?

> Could you please take a look at this set:
> https://github.com/oriansj/M2-Planet/blob/master/test/common_x86/x86_defs.M1

On ARM, it would be (if eax is r0, ebx is r1, ecx is r2, edx is r3, ebp is fp):

DEFINE ADD_IMMEDIATE_to_eax e28000
  Note: ARM immediates are 8 bit value and 4 bit rotation.  The above 
hard-codes the rotation to 0.

DEFINE ADD_IMMEDIATE_to_ebp e28bb0
  Note: ARM immediates are 8 bit value and 4 bit rotation.  The above 
hard-codes the rotation to 0.

DEFINE ADD_eax_to_ebx e0811000
DEFINE ADD_ebp_to_eax e080000b
DEFINE ADD_ebx_to_eax e0800001

DEFINE AND_eax_ebx
  Where's the target?
  If the target is eax, e0000001.
  If the target is ebx, e0011000.

DEFINE CALL_IMMEDIATE
  That's difficult.  Need to use a scratch register.

DEFINE CALL_eax
  Store the current %pc (on ARM, that's usually stored in %lr; for x86 compat, 
we could push it: e52df004 # That's push {%pc})
  After it, use an absolute jump.

DEFINE CMP
  Compare what with what?

DEFINE COPY_eax_to_ebx e1a01000
DEFINE COPY_eax_to_ecx e1a02000

DEFINE COPY_ebp_to_eax e1a0000b
DEFINE COPY_ebx_to_eax e1a00001
DEFINE COPY_ebx_to_edx e1a03001
DEFINE COPY_ecx_to_ebp e1a0200b

DEFINE COPY_edi_to_ebp
  I have no idea what ARM register would correspond to di.
  If %r5, e1a0b005.

DEFINE COPY_esp_to_ebp e1a0b00d
DEFINE COPY_esp_to_ecx e1a0200d
DEFINE COPY_esp_to_edi
  I have no idea what ARM register would correspond to di.
  If %r5, e1a0500b.

DEFINE DIVIDE_eax_by_ebx_into_eax
  ARM division instruction does not exist.  It's possible to use UMULL for a 
lot of special cases.

DEFINE INT_80 ef000000 # That's svc     0x00000000, the ARM equivalent.

DEFINE JUMP e590f000 # LDR %pc, [%r0]
  Is it immediate and direct?  That would be "B".
  Is that an absolute jump? Then not "B" :)

DEFINE JUMP_EQ 0a  # and a 24 bit displacement
DEFINE JUMP_NE 1a  # and a 24 bit displacement

DEFINE JUMP_EQ8
  What's that?

DEFINE JUMP_NE8
  What's that?

DEFINE LOAD_BASE_ADDRESS_eax
  What's that?

DEFINE LOAD_BYTE
  To where?
  From where?
  Usually LDRB %r0, [%r1], or LDRSB %r0, [%r1] for signed byte.

DEFINE LOAD_EFFECTIVE_ADDRESS
  CISC

DEFINE LOAD_EFFECTIVE_ADDRESS_ebx
  CISC

DEFINE LOAD_EFFECTIVE_ADDRESS_ecx
  CISC

DEFINE LOAD_EFFECTIVE_ADDRESS_edx
  CISC

DEFINE LOAD_ESP_IMMEDIATE_into_eax
  What does that do?
  If eax = *(esp + immediate, e59d00 # ldr     %r0, [%sp, #xx]; Assuming 8 bit 
immediate follows.  Rotation hardcoded to 0.

DEFINE LOAD_IMMEDIATE_eax e3a000
  Note: ARM immediates are 8 bit value and 4 bit rotation.  The above 
hard-codes the rotation to 0.

DEFINE LOAD_IMMEDIATE_ebx e3a010
  Note: ARM immediates are 8 bit value and 4 bit rotation.  The above 
hard-codes the rotation to 0.

DEFINE LOAD_IMMEDIATE_edx e3a030
  Note: ARM immediates are 8 bit value and 4 bit rotation.  The above 
hard-codes the rotation to 0.

DEFINE LOAD_INTEGER
  What does that mean?

DEFINE LOAD_INTEGER_ebx
  What does that mean?

DEFINE LOAD_INTEGER_ecx
  What does that mean?

DEFINE LOAD_INTEGER_edx
  What does that mean?

DEFINE MODULUS_eax_from_ebx_into_ebx
  ARM division instruction does not exist.  It's possible to use UMULL for a 
lot of special cases.

DEFINE MOVEZBL 0FB6C0
  Zero-Extend which register?
  UXTB would zero-extend one register into another register (can also specify 
the same register)
  
DEFINE MOVE_ebx_to_eax e1a00001
DEFINE MOVE_ecx_to_eax e1a00002
DEFINE MOVE_edx_to_eax e1a00003
DEFINE MULTIPLY_eax_by_ebx_into_eax
  UMULL in some way

DEFINE NOP e1a00000
DEFINE NOT_eax
  Is the result supposed to be 2^32 - 1 - eax?

DEFINE OR_eax_ebx 09D8
  Which register is the target?
  If eax, e1800001.
  If ebx, e1811000.
  
DEFINE POP_eax e49d0004
DEFINE POP_ebx e49d1004
DEFINE POP_ebp e49db004
DEFINE POP_edi 
  I have no idea which ARM register corresponds to that.
  If %r5, e49d5004.

DEFINE PUSH_eax e52d0004
DEFINE PUSH_ebx e52d1004
DEFINE PUSH_ebp e52db004
DEFINE PUSH_edi
  I have no idea which ARM register corresponds to that.
  If %r5, e52d5004.

DEFINE RETURN C3
  That depends on whether you want to emulate x86 semantics or doing it the ARM 
way.
  For the ARM way, e1a0f00e mov %pc, %lr.
  For the x86 semantics: e49df004 pop {%pc}, and I'm not sure that the 
displacement is correct then.

DEFINE SAL_eax_Immediate8
  No idea what an "arithmetic" LEFT shift does differently compared to a 
logical left shift.

DEFINE SAL_eax_cl
  No idea what an "arithmetic" LEFT shift does differently compared to a 
logical left shift.

DEFINE SAR_eax_cl e1a00250 # asr     r0, r0, r2
  It also only uses the LSB of r2.

DEFINE SETE
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00000 # mov %r0, #0
  and then 03a00001 # moveq %r0, #1

DEFINE SETLE
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00000 # mov %r0, #0
  and then d3a00001 # movle %r0, #1

DEFINE SETL
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00001 # mov %r0, #1
  and then a3a00000 # movge %r0, #0

DEFINE SETGE
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00000 # mov %r0, #0
  and then a3a00001 # movge %r0, #1

DEFINE SETG 0F9FC0
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00001 # mov %r0, #1
  and then d3a00000 # movle %r0, #0

DEFINE SETNE 0F95C0
  Which register?
  ARM has conditions in each instruction, so this need never comes up.
  You could do e3a00000 # mov %r0, #0
  and then 13a00001 # movne %r0, #1

DEFINE STORE_CHAR
  Store where?
  How big is a char?
  Is it assumed that it's an immediate?
  Is it storing only one byte into the memory cell or is it padding it?

DEFINE STORE_eax_into_ESP_IMMEDIATE8 e58b00
  The immediate follows (8 bit).
  It does *(esp + immediate) = eax.

DEFINE STORE_INTEGER
  Store where?
  How big is an integer?

DEFINE SUBTRACT_eax_from_ebx_into_ebx e0411000
DEFINE TEST
  Test what with what? There's a TST instruction, but there are a lot of 
variants.

DEFINE XCHG_eax_ebx
  That... is difficult without a scratch register.
  I guess push {%r0}, push {%r1}, pop {%r0}, pop {%r1}

DEFINE XOR_ebx_eax_into_eax e0200001 # eor     r0, r0, r1

> As Getting M2-Planet to ARM will help get Mescc's bootstrap on ARM as
> well and they can share the exact same operations.

Cool!

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