Bug with repeated instances of per-target variable assignment

[David Zuhn]

This is GNU make 3.79.1, running on Solaris 2.6.

Using this Makefile (tabs may be lost in the mail)

CC = gcc

INCS = -Iblorch

foo.o: INCS += -Ifoo
foo.o: INCS += -Ibar
foo.o: INCS += -Ibaz

foo: foo.o
        $(CC) $(LIBS) $^ -o $@

foo.o: foo.c
        $(CC) $(INCS) -c $< -o $@

foo.c:
        echo "int main() { return 0; }" > foo.c


when I run a 'make', the command contains -Iblorch -Ibaz,  with no reference
to the additional assignments of -Ifoo or -Ibar.    I was expecting to see an
expansion of $(INCS) as "-Iblorch -Ifoo -Ibar -Ibaz".

Considering that if I specify multiple prerequisites for foo.o as follows:

foo.o: bar.h
foo.o: baz.h

each of the listed files is added to the dependency graph, I was expecting
variable assignments to happen in this fashion as well.   The manual states as
follows:

   All variables that appear within the variable-assignment are evaluated 
within the
   context of the target: thus, any previously-defined target-specific 
variable values
   will be in effect   (make.info, node "Target-specific variable values)



Note that I can have multiple variables assigned using the same target name

foo.o:  FOO += -IFOO
foo.o:  INCS += -IFOO

will append -IFOO to each of $(FOO) and $(INCS), but the previous example 
doesn't
process each invocation of the variable assignment.




david d zuhn
address@hidden