[Bug gas/30582] New: RISC-V assembler: check restrictions on LR/SC sequences

[skvadrik at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30582

            Bug ID: 30582
           Summary: RISC-V assembler: check restrictions on LR/SC
                    sequences
           Product: binutils
           Version: unspecified
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: gas
          Assignee: unassigned at sourceware dot org
          Reporter: skvadrik at gmail dot com
  Target Milestone: ---

Hi! This is a feature request.

The restrictions on LR/SC sequences that guarantee progress ("10.3. Eventual
Success of Store-Conditional Instructions" in the unprivileged RISC-V spec)
state that:

• The loop comprises only an LR/SC sequence and code to retry the sequence in
the case of failure, and must comprise at most 16 instructions placed
sequentially in memory.

• An LR/SC sequence begins with an LR instruction and ends with an SC
instruction. The dynamic code executed between the LR and SC instructions can
only contain instructions from the base ''I'' instruction set, excluding loads,
stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM
instructions. If the ''C'' extension is supported, then compressed forms of the
aforementioned ''I'' instructions are also permitted.

• The code to retry a failing LR/SC sequence can contain backwards jumps and/or
branches to repeat the LR/SC sequence, but otherwise has the same constraint as
the code between the LR and SC.

• The LR and SC addresses must lie within a memory region with the LR/SC
eventuality property. The execution environment is responsible for
communicating which regions have this property.

• The SC must be to the same effective address and of the same data size as the
latest LR executed by the same hart.

I wonder if the assembler could help verify some of these.

E.g. the limit is 16 instructions, but this gets difficult to ensure if we use
pseudo-instructions like LI (load immediate) which, depending on the immediate,
may unfold to a different number of instructions. Assembler knows how many
instructions LI unfolds to, so it can probably do the check. Alternatively it
could provide a directive that asserts that a sequence of instructions has a
given length and errors otherwise.

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