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[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target

From: henrik at brixandersen dot dk
Subject: [Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness
Date: Mon, 03 Aug 2020 19:52:38 +0000


Henrik Brix Andersen <henrik at brixandersen dot dk> changed:

           What    |Removed                     |Added
                 CC|                            |henrik at brixandersen dot dk

--- Comment #1 from Henrik Brix Andersen <henrik at brixandersen dot dk> ---
I can confirm this bug. I too was trying out the --verilog-data-width option,
here on arm-zephyr-eabi. This is a little endian target, but the Verilog memory
hex dump produced is in big-endian format.

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