[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Bug binutils/25202] New: objcopy --verilog-data-width doesn't respect t
olof.kindgren at gmail dot com
[Bug binutils/25202] New: objcopy --verilog-data-width doesn't respect target's endianness
Mon, 18 Nov 2019 11:21:18 +0000
Bug ID: 25202
Summary: objcopy --verilog-data-width doesn't respect target's
Assignee: unassigned at sourceware dot org
Reporter: olof.kindgren at gmail dot com
Target Milestone: ---
I just tried binutils 2.33.1 compiled for riscv32-unknown-elf to test
https://sourceware.org/bugzilla/show_bug.cgi?id=19921. Unfortunately it doesn't
match what I was expecting to see.
Problem is that it will always use big endian output since (I think) the
bfd_target for verilog has BFD_ENDIAN_UNKNOWN. I was expecting it to use the
endianness of the source architecture.
I got around it by setting target byte order of the verilog_vec bfd_target to
BFD_ENDIAN_LITTLE but I don't have enough experience with binutils to see where
the correct fix should be.
You are receiving this mail because:
You are on the CC list for the bug.
|[Prev in Thread]
||[Next in Thread]|
- [Bug binutils/25202] New: objcopy --verilog-data-width doesn't respect target's endianness,
olof.kindgren at gmail dot com <=