[Bug gold/18010] --gc-sections breaks LLVM's TableGen on ppc64

[amodra at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=18010

--- Comment #1 from Alan Modra <amodra at gmail dot com> ---
We have a bunch of strings in a string merge section
 .section .rodata.str1.8,"aMS",@progbits,1
all nicely aligned to 8 byte boundaries (as you'd expect from the .8 in the
name).  Somehow the alignment isn't respected and we end up with misaligned
strings.  Since a powerpc64 ld reg+offset form address must be a multiple of 4,
we lose low bits of the address.

This is the code reading the "      break;\n" string.  .LC84 happens to be
defined at .rodata.str1.8+0x570.

    1d50:       3d 02 00 00     addis   r8,r2,0
                        1d52: R_PPC64_TOC16_HA  .LC84+0x8
    1d54:       80 e8 00 00     lwz     r7,0(r8)
                        1d56: R_PPC64_TOC16_LO  .LC84+0x8
    1d58:       3d 02 00 00     addis   r8,r2,0
                        1d5a: R_PPC64_TOC16_HA  .LC84+0xc
    1d5c:       89 28 00 00     lbz     r9,0(r8)
                        1d5e: R_PPC64_TOC16_LO  .LC84+0xc
    1d60:       3d 02 00 00     addis   r8,r2,0
                        1d62: R_PPC64_TOC16_HA  .rodata.str1.8+0x570
    1d64:       90 ea 00 08     stw     r7,8(r10)
    1d68:       99 2a 00 0c     stb     r9,12(r10)
    1d6c:       e9 28 00 00     ld      r9,0(r8)
                        1d6e: R_PPC64_TOC16_LO_DS       .rodata.str1.8+0x570

This is linked to
    100fdad0:   3d 02 ff fb     addis   r8,r2,-5
    100fdad4:   80 e8 7b 22     lwz     r7,31522(r8)
    100fdad8:   3d 02 ff fb     addis   r8,r2,-5
    100fdadc:   89 28 7b 26     lbz     r9,31526(r8)
    100fdae0:   3d 02 ff fb     addis   r8,r2,-5
    100fdae4:   90 ea 00 08     stw     r7,8(r10)
    100fdae8:   99 2a 00 0c     stb     r9,12(r10)
    100fdaec:   e9 28 7b 18     ld      r9,31512(r8)

For starters, I'll be committing a patch that makes gold complain if LO_DS
relocs attempt to apply a misaligned value.

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