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Re: AW: AW: [avr-libc-dev] Additional instruction patterns for or more e
From: |
Denis Chertykov |
Subject: |
Re: AW: AW: [avr-libc-dev] Additional instruction patterns for or more efficient code using mixed QI/HI/SI expressions |
Date: |
13 Dec 2004 12:09:38 +0300 |
User-agent: |
Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 |
Björn Haase <address@hidden> writes:
> Hy Denis,
>
> Thank's for reviewing the code fragments
>
> >Some your new patterns are right some are wrong. I suggest to produce
> >the work step by step with small changes.
>
> Consider my suggestions to be the sketch of a basic idea. My suggestion
> is to concentrate on the change in the two "define_expand"s and the
> move patterns first. Possibly one might add the compare patterns as well.
>
> >PS: Righ now I think that better to rewrite many insns for
> > HI,SI,DI modes as splitters to QI mode (naitive AVR) insns.
> > If you want to help then better to concentrate on this.
>
> I agree with you in that this would be a much better solution. The only
> possible disadvantage is, in my opinion, that debugging of optimized code
> would be
> allmost impossible.
Don't worry about debugging. IMHO compiler so smart to resolve such
problems. Many ports (i386,arm, ...) uses splitting.
>
> Before writing so many combined patterns, I have also thought about
> using UNSPECs, eg. for defining adc, sbc, etc. and use splitting of the SI
> instructions.
First ! oly add and sub needed in borrow. xor,and,or,not,neg are very
simple. You can start with one of them.
UNSPEC's is not required for this.
Look at arm port:
(define_insn_and_split "*arm_adddi3"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && !TARGET_CIRRUS"
"#"
"TARGET_ARM && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI (match_dup 4) (match_dup 5))))]
"
{
operands[3] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[5] = gen_highpart (SImode, operands[2]);
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "conds" "clob")
(set_attr "length" "8")]
)
>
> So far, I, however thought that there is no easy way for teaching
> the compiler to actually use them since this would require to get
> rid of all objects with DI/SI and HI mode after the RTL generation
> step.
I mean `splitting' as define_split not as define_expand.
May be better to enable such splitters only after reload pass.
> I thought, that this would make it necessary to add a completely new
> optimizer pass. For implementing this, one would need a deeper
> knowledge of gcc interna than I have.
No special passes !
Denis.
[avr-libc-dev] AW: Register allocator / -fnew-ra issue, Björn Haase, 2004/12/07
RE: [avr-libc-dev] Improved optimizer for mixed 32 / 16 / 8 bitexpressions, Bernard Fouché, 2004/12/02