make variables defined via include

[Harlan Stenn]

Here's what I think is happening.

There's an application that uses libtool.  All of the "places" where
somebody wants to use a library it is specified via $(libfoo_la_LIBDEP), and
we run a wrapper script before we run the first "make" that scans all of the
Makefiles and builds:

 libfoo_la_LIBDEP = <correct builddir>/libfoo.la

and a final section that says:

 ALL_LIB_TARGETS = \
        /builddir/for/libfoo.la \
        /builddir/for/libbar.la \
        ...

and there is a (gloablly included) rule that effectively says:

 $(ALL_LIB_TARGETS):
        cd $(@D) && $(MAKE) $(AM_FLAGS) $(@F)

The goal is to have missing libraries get automatically rebuilt.

In the past we used to .EXPORT_ALL_VARIABLES .  We can no longer do this, as
the environment is too big.

Unfortunately, it now appears that at the time when the Makefile is
initially scanned (by gmake 1.79.1), $(libfoo_la_LIBDEP) is not defined, so
it does not appear as a dependency.  However, when "make" goes to create the
target, $(libfoo_la_LIBDEP) *is* defined, so the link fails because the
library has not yet been built.

Is this making sense?

Any ideas on how to fix the problem?

H