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qemu-riscv (date)
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Last Modified: Tue May 31 2022 23:52:57 -0400
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May 31, 2022
Re: [PATCH] hw/riscv: virt: Generate fw_cfg DT node correctly
,
Alistair Francis
,
23:52
RE: [PATCH] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
,
limingwang (A)
,
23:11
Re: [PATCH] hw/riscv: virt: Generate fw_cfg DT node correctly
,
Alistair Francis
,
22:05
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
22:02
Re: [PATCH v3] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
21:45
[PATCH v2] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
21:37
[PATCH] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
,
Alistair Francis
,
21:36
[PATCH] target/riscv: Wake on VS-level external interrupts
,
Andrew Bresticker
,
17:05
[PATCH v5 3/3] target/riscv: Add vstimecmp support
,
Atish Patra
,
14:04
[PATCH v5 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Atish Patra
,
14:03
[PATCH v5 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
14:03
[PATCH v5 0/3] Implement Sstc extension
,
Atish Patra
,
14:03
[PATCH] qemu: riscv: rvv: fix vmv.v.x for RV32, el64, vl == vl_max
,
Robert Bu
,
09:16
May 30, 2022
[PATCH v3] target/riscv: add support for zmmul extension v0.1
,
Weiwei Li
,
23:08
Re: [PATCH] MAINTAINERS: Add myself as hw/core/uboot_image.h maintainer
,
Alistair Francis
,
20:20
Re: [PATCH v2] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
20:17
Re: [PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Alistair Francis
,
20:12
Re: [PATCH v9 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Alistair Francis
,
20:12
Re: [PATCH] MAINTAINERS: Add myself as hw/core/uboot_image.h maintainer
,
Philippe Mathieu-Daudé
,
11:38
May 27, 2022
Re: [PATCH v4 2/3] target/riscv: Add stimecmp support
,
Atish Kumar Patra
,
18:44
May 26, 2022
Re: [PATCH v2] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
22:08
Re: [PATCH v4 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
22:07
[PATCH] hw/riscv: virt: Generate fw_cfg DT node correctly
,
Atish Patra
,
16:35
Re: [PATCH] target/riscv: fix priv enum
,
Nikita Shubin
,
06:48
Re: [PATCH] target/riscv: fix priv enum
,
Anup Patel
,
06:08
[PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
06:06
[PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
06:06
[PATCH v3 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Anup Patel
,
06:06
[PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest
,
Anup Patel
,
06:06
[PATCH v3 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
06:06
[PATCH] target/riscv: fix priv enum
,
Nikita Shubin
,
04:44
Re: [PATCH v9 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
03:50
Re: [PATCH v9 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
03:35
Re: [PATCH v4 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
03:16
Re: [PATCH v4 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
01:11
May 25, 2022
Re: [PATCH v4 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Alistair Francis
,
20:57
Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
,
Tsukasa OI
,
10:56
[PATCH v2.1 2/3] target/riscv: Make CPU property names lowercase
,
Tsukasa OI
,
10:46
Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
,
Víctor Colombo
,
08:10
Re: [PATCH v9 09/12] target/riscv: Simplify counter predicate function
,
Frank Chang
,
06:24
Re: [PATCH v9 08/12] target/riscv: Add sscofpmf extension support
,
Frank Chang
,
06:21
[PATCH v2 3/3] target/riscv: Deprecate capitalized property names
,
Tsukasa OI
,
05:55
[PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties
,
Tsukasa OI
,
05:55
[PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)
,
Tsukasa OI
,
05:55
[PATCH v2 2/3] target/riscv: Make CPU property names lowercase
,
Tsukasa OI
,
05:55
May 24, 2022
Re: [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes
,
Alistair Francis
,
18:19
Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e devices
,
Jim Shu
,
16:10
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Andrea Bolognani
,
11:56
Re: [PATCH v2 2/5] target/riscv: Disable "G" by default
,
Víctor Colombo
,
11:48
Re: [PATCH] .gitlab-ci.d/container-cross: Fix RISC-V container dependencies / stages
,
Alex Bennée
,
11:46
Re: [PATCH v2] target/riscv: add support for zmmul extension v0.1
,
Víctor Colombo
,
10:38
Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
08:19
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
08:10
[PATCH] .gitlab-ci.d/container-cross: Fix RISC-V container dependencies / stages
,
Thomas Huth
,
05:32
Re: [PATCH v2 2/5] target/riscv: Disable "G" by default
,
Tsukasa OI
,
05:07
[PATCH v2] target/riscv: add support for zmmul extension v0.1
,
Weiwei Li
,
00:53
Re: [PATCH] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
00:19
May 23, 2022
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Patra
,
23:17
Re: [PATCH] target/riscv: add support for zmmul extension v0.1
,
Weiwei Li
,
22:25
[PATCH v9 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
19:51
[PATCH v9 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
19:51
[PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
19:51
[PATCH v9 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
19:51
[PATCH v9 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
19:51
[PATCH v9 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
19:51
[PATCH v9 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
19:51
[PATCH v9 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
19:51
[PATCH v9 03/12] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
19:51
[PATCH v9 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
19:51
[PATCH v9 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
19:51
[PATCH v9 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
19:51
[PATCH v9 00/12] Improve PMU support
,
Atish Patra
,
19:51
Re: [PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Alistair Francis
,
19:49
Re: [PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Alistair Francis
,
18:01
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Alistair Francis
,
17:52
Re: [RESEND PATCH v2] target/riscv: Fix typo of mimpid cpu option
,
Alistair Francis
,
17:47
Re: [PATCH qemu v18 02/16] target/riscv: rvv: Prune redundant access_type parameter passed
,
Alistair Francis
,
17:40
Re: [PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices
,
Alistair Francis
,
17:39
Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
17:38
Re: [PATCH] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
17:16
Re: [PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Hongren (Zenithal) Zheng
,
12:51
[RESEND PATCH v2] target/riscv: Fix typo of mimpid cpu option
,
frank . chang
,
11:32
[PATCH v2] target/riscv: Fix typo of mimpid cpu option
,
frank . chang
,
11:18
Re: [PATCH] target/riscv: add support for zmmul extension v0.1
,
Weiwei Li
,
04:10
Re: [RFC PATCH 1/1] target/riscv: Make property names lowercase
,
Alistair Francis
,
02:37
Re: [PATCH] target/riscv: add support for zmmul extension v0.1
,
Alistair Francis
,
02:35
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
02:00
May 22, 2022
Re: [PATCH v4] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Alistair Francis
,
20:16
Re: [PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Alistair Francis
,
19:22
Re: [PATCH] target/riscv: Fix typo of mimpid cpu option
,
Alistair Francis
,
19:21
May 20, 2022
[PATCH] target/riscv: Fix typo of mimpid cpu option
,
frank . chang
,
05:15
May 19, 2022
Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node
,
Dylan Reid
,
16:45
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Kumar Patra
,
14:16
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
11:07
Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node
,
Anup Patel
,
11:04
Re: [PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Jiatai He
,
09:47
May 18, 2022
Re: [PATCH 03/18] block: Change blk_{pread,pwrite}() param order
,
Eric Blake
,
10:06
[PATCH] target/riscv: add zicsr/zifencei to isa_string
,
Hongren (Zenithal) Zheng
,
09:36
Re: [PATCH 01/18] block: Make blk_{pread,pwrite}() return 0 on success
,
Eric Blake
,
08:57
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Peter Maydell
,
06:47
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Daniel P . Berrangé
,
04:26
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Patra
,
02:39
Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
02:08
May 17, 2022
[PATCH] target/riscv: add support for zmmul extension v0.1
,
Weiwei Li
,
21:54
[PATCH v4] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Weiwei Li
,
21:26
Re: [PATCH v3] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Alistair Francis
,
17:34
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
16:54
Re: [PATCH 02/18] block: Add a 'flags' param to blk_pread()
,
Greg Kurz
,
12:27
Re: [PATCH 02/18] block: Add a 'flags' param to blk_pread()
,
Paolo Bonzini
,
10:20
Re: [PATCH 01/18] block: Make blk_{pread,pwrite}() return 0 on success
,
Greg Kurz
,
10:03
[PATCH 01/18] block: Make blk_{pread,pwrite}() return 0 on success
,
Alberto Faria
,
09:34
[PATCH 03/18] block: Change blk_{pread,pwrite}() param order
,
Alberto Faria
,
09:34
[PATCH 02/18] block: Add a 'flags' param to blk_pread()
,
Alberto Faria
,
09:34
[PATCH 00/18] Make block-backend-io.h API more consistent
,
Alberto Faria
,
09:34
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Daniel P . Berrangé
,
04:52
[PATCH v3] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Weiwei Li
,
03:27
No disassembly of RISC-V RVV instructions?
,
Robert Bu
,
01:28
Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node
,
Alistair Francis
,
01:11
Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs
,
Alistair Francis
,
01:08
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
01:04
Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs
,
Weiwei Li
,
01:02
Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
,
Weiwei Li
,
00:49
Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
,
Alistair Francis
,
00:17
[PATCH 2/2] target/riscv: Run extension checks for all CPUs
,
Alistair Francis
,
00:11
[PATCH 1/2] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
00:11
[PATCH 0/2] target/riscv: Cleanup exposed CPU properties
,
Alistair Francis
,
00:11
May 16, 2022
[PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
,
Weiwei Li
,
22:20
[PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Weiwei Li
,
22:19
Re: [PATCH 0/5] target/riscv: Enhanced ISA extension checks
,
Alistair Francis
,
22:18
Re: [PATCH v2 0/2] hw/riscv: Make CPU config error handling generous
,
Alistair Francis
,
21:58
Re: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks
,
Alistair Francis
,
21:37
Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
,
Weiwei Li
,
21:34
Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Weiwei Li
,
21:33
Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
,
Alistair Francis
,
20:54
Re: [PATCH v2 4/5] target/riscv: FP extension requirements
,
Alistair Francis
,
20:52
Re: [PATCH v2 3/5] target/riscv: Change "G" expansion
,
Alistair Francis
,
20:41
Re: [PATCH 2/5] target/riscv: Disable "G" by default
,
Alistair Francis
,
20:40
Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion
,
Alistair Francis
,
20:38
Re: [PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
,
Alistair Francis
,
20:37
Re: [PATCH v2 1/2] hw/riscv: Make CPU config error handling generous (virt/spike)
,
Alistair Francis
,
20:36
Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
,
Alistair Francis
,
20:34
Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Alistair Francis
,
20:23
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Alistair Francis
,
20:16
Re: [PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement
,
Alistair Francis
,
19:28
Re: [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Alistair Francis
,
19:25
Re: [PATCH] hw/riscv: virt: Avoid double FDT platform node
,
Alistair Francis
,
19:23
Re: [PATCH v2 2/2] target/riscv: Add short-isa-string option
,
Alistair Francis
,
19:20
Re: [PATCH v2 1/2] target/riscv: Move Zhinx* extensions on ISA string
,
Alistair Francis
,
19:20
Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
,
Alistair Francis
,
19:10
Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
,
Alistair Francis
,
18:41
Re: [PATCH v2 2/5] target/riscv: Disable "G" by default
,
Víctor Colombo
,
14:04
Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion
,
Víctor Colombo
,
13:58
Re: [PATCH 1/5] target/riscv: Fix "G" extension expansion typing
,
Víctor Colombo
,
13:39
May 15, 2022
[PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
,
Weiwei Li
,
23:34
[PATCH 2/2] target/riscv: disable zb* extensions by default
,
Weiwei Li
,
23:34
Re: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks
,
Weiwei Li
,
23:12
Re: [PATCH v2 4/5] target/riscv: FP extension requirements
,
Weiwei Li
,
11:23
Re: [PATCH v2 4/5] target/riscv: FP extension requirements
,
Tsukasa OI
,
10:45
Re: [PATCH v2 4/5] target/riscv: FP extension requirements
,
Weiwei Li
,
10:37
May 14, 2022
[PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks
,
Tsukasa OI
,
22:56
[PATCH v2 4/5] target/riscv: FP extension requirements
,
Tsukasa OI
,
22:56
[PATCH v2 3/5] target/riscv: Change "G" expansion
,
Tsukasa OI
,
22:56
[PATCH v2 2/5] target/riscv: Disable "G" by default
,
Tsukasa OI
,
22:56
[PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion
,
Tsukasa OI
,
22:56
[PATCH v2 0/5] target/riscv: Enhanced ISA extension checks
,
Tsukasa OI
,
22:56
[PATCH qemu v5 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
~eopxd
,
11:19
[PATCH qemu v5 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
~eopxd
,
11:19
[PATCH qemu v5 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
~eopxd
,
11:19
[PATCH qemu v5 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
~eopxd
,
11:19
[PATCH qemu v5 00/10] Add mask agnostic behavior for rvv instructions
,
~eopxd
,
11:19
[PATCH qemu v5 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
11:19
[PATCH qemu v5 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
~eopxd
,
11:19
[PATCH qemu v5 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
~eopxd
,
11:19
[PATCH qemu v5 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
~eopxd
,
11:19
[PATCH qemu v5 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
~eopxd
,
11:19
[PATCH qemu v5 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
~eopxd
,
11:19
Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation
,
Frank Chang
,
03:46
[PATCH v2 1/2] hw/riscv: Make CPU config error handling generous (virt/spike)
,
Tsukasa OI
,
02:30
[PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
,
Tsukasa OI
,
02:30
[PATCH v2 0/2] hw/riscv: Make CPU config error handling generous
,
Tsukasa OI
,
02:30
Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
,
Anup Patel
,
00:42
May 13, 2022
Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
,
Frank Chang
,
22:21
[PATCH] hw/intc: Pass correct hartid while updating mtimecmp
,
Atish Patra
,
18:15
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Atish Patra
,
14:45
Re: [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Atish Patra
,
14:25
Re: [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest
,
Atish Patra
,
14:24
Re: [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking
,
Atish Patra
,
14:20
[PATCH v4 3/3] target/riscv: Add vstimecmp support
,
Atish Patra
,
14:18
[PATCH v4 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
14:18
[PATCH v4 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Atish Patra
,
14:18
[PATCH v4 0/3] Implement Sstc extension
,
Atish Patra
,
14:17
Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
Weiwei Li
,
12:19
Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
Weiwei Li
,
12:09
Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Kumar Patra
,
11:58
[PATCH qemu v4 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
~eopxd
,
07:58
[PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
~eopxd
,
07:58
[PATCH qemu v4 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
~eopxd
,
07:58
[PATCH qemu v4 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
~eopxd
,
07:58
[PATCH qemu v4 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
~eopxd
,
07:58
[PATCH qemu v4 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
07:58
[PATCH qemu v4 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
~eopxd
,
07:58
[PATCH qemu v4 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
~eopxd
,
07:58
[PATCH qemu v4 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
~eopxd
,
07:58
[PATCH qemu v4 00/10] Add mask agnostic behavior for rvv instructions
,
~eopxd
,
07:58
[PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
~eopxd
,
07:58
[PATCH qemu v18 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
07:50
[PATCH qemu v18 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
07:50
[PATCH qemu v18 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
07:50
[PATCH qemu v18 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
07:50
[PATCH qemu v18 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
07:50
[PATCH qemu v18 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
07:50
[PATCH qemu v18 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
07:50
[PATCH qemu v18 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
07:50
[PATCH qemu v18 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
07:50
[PATCH qemu v18 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
07:50
[PATCH qemu v18 05/16] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
07:50
[PATCH qemu v18 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
07:50
[PATCH qemu v18 03/16] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
07:50
[PATCH qemu v18 04/16] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
07:50
[PATCH qemu v18 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
07:50
[PATCH qemu v18 02/16] target/riscv: rvv: Prune redundant access_type parameter passed
,
~eopxd
,
07:50
[PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
07:49
Re: [RFC PATCH v4 1/4] target/riscv: Add smstateen support
,
Tsukasa OI
,
05:55
[PATCH 2/2] target/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
,
Tsukasa OI
,
05:47
[PATCH 1/2] target/riscv: Make CPU config error handling generous (virt/spike)
,
Tsukasa OI
,
05:47
[PATCH 0/2] hw/riscv: Make CPU config error handling generous
,
Tsukasa OI
,
05:47
[RFC PATCH 1/1] target/riscv: Make property names lowercase
,
Tsukasa OI
,
05:47
[RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases
,
Tsukasa OI
,
05:47
[PATCH 5/5] target/riscv: Move/refactor ISA extension checks
,
Tsukasa OI
,
05:46
[PATCH 4/5] target/riscv: FP extension requirements
,
Tsukasa OI
,
05:46
[PATCH 3/5] target/riscv: Change "G" expansion
,
Tsukasa OI
,
05:46
[PATCH 2/5] target/riscv: Disable "G" by default
,
Tsukasa OI
,
05:46
[PATCH 1/5] target/riscv: Fix "G" extension expansion typing
,
Tsukasa OI
,
05:46
[PATCH 0/5] target/riscv: Enhanced ISA extension checks
,
Tsukasa OI
,
05:46
[RFC PATCH v4 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
04:52
[RFC PATCH v4 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
04:52
[RFC PATCH v4 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
04:52
[RFC PATCH v4 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
04:51
[RFC PATCH v4 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
04:51
Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation
,
Frank Chang
,
02:30
May 12, 2022
Re: [PATCH v3 3/3] target/riscv: Add vstimecmp support
,
Atish Kumar Patra
,
21:59
Re: [PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions
,
Weiwei Li
,
21:32
[PATCH] hw/riscv: virt: Avoid double FDT platform node
,
Dylan Reid
,
16:04
Re: [PATCH 1/1] Add Zihintpause support
,
Dao Lu
,
13:58
Re: [PATCH 1/1] Add Zihintpause support
,
Tsukasa OI
,
08:21
Re: [PATCH 1/1] Add Zihintpause support
,
Heiko Stübner
,
06:52
[PATCH qemu v3 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
~eopxd
,
04:55
[PATCH qemu v3 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
~eopxd
,
04:55
[PATCH qemu v3 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
~eopxd
,
04:55
[PATCH qemu v3 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
~eopxd
,
04:55
[PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions
,
~eopxd
,
04:55
[PATCH qemu v3 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
~eopxd
,
04:55
[PATCH qemu v3 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
~eopxd
,
04:55
[PATCH qemu v3 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
~eopxd
,
04:55
[PATCH qemu v3 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
~eopxd
,
04:55
[PATCH qemu v3 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
04:55
[PATCH qemu v3 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
~eopxd
,
04:55
[PATCH qemu v17 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
04:27
[PATCH qemu v17 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
04:27
[PATCH qemu v17 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
04:27
[PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
04:27
[PATCH qemu v17 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
04:27
[PATCH qemu v17 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
04:27
[PATCH qemu v17 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
04:27
[PATCH qemu v17 02/16] target/riscv: rvv: Prune redundant access_type parameter passed
,
~eopxd
,
04:27
[PATCH qemu v17 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
04:26
[PATCH qemu v17 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
04:26
[PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
04:26
[PATCH qemu v17 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
04:26
[PATCH qemu v17 03/16] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
04:26
[PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
04:26
[PATCH qemu v17 05/16] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
04:26
[PATCH qemu v17 00/16] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
04:26
[PATCH qemu v17 04/16] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
04:26
Re: [PATCH v3 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Anup Patel
,
00:50
Re: [PATCH v3 3/3] target/riscv: Add vstimecmp support
,
Anup Patel
,
00:48
Re: [PATCH v3 2/3] target/riscv: Add stimecmp support
,
Anup Patel
,
00:47
May 11, 2022
Re: [PATCH qemu v16 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
Weiwei Li
,
22:56
[PATCH v8 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
18:00
[PATCH v8 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
18:00
[PATCH v8 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
18:00
[PATCH v8 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
18:00
[PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
18:00
[PATCH v8 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
18:00
[PATCH v8 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
18:00
[PATCH v8 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
18:00
[PATCH v8 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
18:00
[PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
18:00
[PATCH v8 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
18:00
[PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
18:00
[PATCH v8 00/12] Improve PMU support
,
Atish Patra
,
18:00
[PATCH qemu v16 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
13:03
[PATCH qemu v16 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
13:03
[PATCH qemu v16 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
13:03
[PATCH qemu v16 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
13:03
[PATCH qemu v16 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
13:03
[PATCH qemu v16 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
13:03
[PATCH qemu v16 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
13:03
[PATCH qemu v16 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
13:03
[PATCH qemu v16 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
13:03
[PATCH qemu v16 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
13:03
[PATCH qemu v16 04/15] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
13:03
[PATCH qemu v16 02/15] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
13:03
[PATCH qemu v16 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
13:03
[PATCH qemu v16 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
13:03
[PATCH qemu v16 00/15] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
13:03
[PATCH qemu v16 03/15] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
13:03
[PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices
,
Anup Patel
,
10:47
[PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
10:47
[PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Anup Patel
,
10:46
[PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest
,
Anup Patel
,
10:46
[PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
10:46
[PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
,
Anup Patel
,
10:46
[PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Anup Patel
,
10:46
[PATCH v2 1/8] target/riscv: Fix csr number based privilege checking
,
Anup Patel
,
10:46
[PATCH v2 0/8] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
10:46
May 10, 2022
Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
Weiwei Li
,
22:54
Re: [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
Weiwei Li
,
22:39
Re: [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
Weiwei Li
,
22:39
Re: [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
Weiwei Li
,
22:37
Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
Weiwei Li
,
22:29
Re: [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
Weiwei Li
,
22:26
Re: [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
Weiwei Li
,
22:24
Re: [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
Weiwei Li
,
22:09
Re: [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
Weiwei Li
,
22:08
Re: [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
Weiwei Li
,
22:06
Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
Weiwei Li
,
22:00
[PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
~eopxd
,
14:26
[PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
~eopxd
,
14:26
[PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
~eopxd
,
14:26
[PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
~eopxd
,
14:26
[PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
14:26
[PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
~eopxd
,
14:26
[PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
~eopxd
,
14:26
[PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
~eopxd
,
14:26
[PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions
,
~eopxd
,
14:26
[PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
~eopxd
,
14:26
[PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
~eopxd
,
14:26
Re: [PATCH 1/1] Add Zihintpause support
,
Dao Lu
,
13:42
Re: [PATCH qemu v15 00/15] Add tail agnostic behavior for rvv instructions
,
eop Chen
,
12:55
[PATCH qemu v15 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
12:50
[PATCH qemu v15 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
12:50
[PATCH qemu v15 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
12:50
[PATCH qemu v15 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
12:50
[PATCH qemu v15 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
12:50
[PATCH qemu v15 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
12:50
[PATCH qemu v15 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
12:50
[PATCH qemu v15 04/15] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
12:50
[PATCH qemu v15 03/15] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
12:50
[PATCH qemu v15 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
12:50
[PATCH qemu v15 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
12:50
[PATCH qemu v15 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
12:50
[PATCH qemu v15 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
12:50
[PATCH qemu v15 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
12:50
[PATCH qemu v15 02/15] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
12:50
[PATCH qemu v15 00/15] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
12:49
Re: [PATCH 1/1] Add Zihintpause support
,
Richard Henderson
,
11:43
[PATCH 0/1] Add Zihintpause support
,
Dao Lu
,
09:57
[PATCH 1/1] Add Zihintpause support
,
Dao Lu
,
09:57
Re: QEMU 32-bit vs. 64-bit binaries
,
Peter Maydell
,
08:25
Re: QEMU 32-bit vs. 64-bit binaries
,
Gerd Hoffmann
,
08:21
Re: [PATCH qemu v14 00/15] Add tail agnostic behavior for rvv instructions
,
Alistair Francis
,
07:42
[PATCH v2 2/2] target/riscv: Add short-isa-string option
,
Tsukasa OI
,
07:29
[PATCH v2 1/2] target/riscv: Move Zhinx* extensions on ISA string
,
Tsukasa OI
,
07:29
[PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement
,
Tsukasa OI
,
07:29
Re: [PATCH 1/2] target/riscv: Tentatively remove Zhinx* from ISA extension string
,
Tsukasa OI
,
07:25
Re: [PATCH 2/2] target/riscv: Add short-isa-string option
,
Tsukasa OI
,
07:20
Re: QEMU 32-bit vs. 64-bit binaries
,
BALATON Zoltan
,
06:14
Re: [PATCH qemu v14 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
Alistair Francis
,
06:13
Re: [PATCH qemu v14 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
Alistair Francis
,
06:12
Re: [PATCH qemu v14 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
Alistair Francis
,
06:01
Re: [PATCH qemu v14 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
Alistair Francis
,
05:59
Re: [PATCH qemu v14 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
Alistair Francis
,
05:57
Re: [PATCH qemu v14 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
Alistair Francis
,
05:49
Re: QEMU 32-bit vs. 64-bit binaries
,
Peter Maydell
,
05:47
Re: [PATCH qemu v14 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
Alistair Francis
,
05:37
Re: [PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
Alistair Francis
,
05:34
Re: QEMU 32-bit vs. 64-bit binaries
,
Thomas Huth
,
05:31
Re: QEMU 32-bit vs. 64-bit binaries
,
Dr. David Alan Gilbert
,
05:22
Re: [PATCH qemu v14 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
Alistair Francis
,
05:20
Re: QEMU 32-bit vs. 64-bit binaries
,
Peter Maydell
,
05:14
Re: [PATCH qemu v14 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
Alistair Francis
,
05:02
Re: QEMU 32-bit vs. 64-bit binaries
,
Thomas Huth
,
05:01
Re: [PATCH qemu v14 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
Alistair Francis
,
05:00
Re: QEMU 32-bit vs. 64-bit binaries
,
Markus Armbruster
,
04:54
Re: [PATCH qemu v14 04/15] target/riscv: rvv: Add tail agnostic for vv instructions
,
Alistair Francis
,
04:51
Re: QEMU 32-bit vs. 64-bit binaries (was: [PATCH] mos6522: fix linking error when CONFIG_MOS6522 is not set)
,
Alistair Francis
,
04:27
QEMU 32-bit vs. 64-bit binaries (was: [PATCH] mos6522: fix linking error when CONFIG_MOS6522 is not set)
,
Thomas Huth
,
04:03
May 09, 2022
[PATCH v3 3/3] target/riscv: Add vstimecmp support
,
Atish Patra
,
17:28
[PATCH v3 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Atish Patra
,
17:28
[PATCH v3 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
17:28
[PATCH v3 0/3] Implement Sstc extension
,
Atish Patra
,
17:28
Re: [PATCH 1/3] target/riscv: Don't force update priv spec version to latest
,
Atish Patra
,
16:02
Re: [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Atish Patra
,
15:54
Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking
,
Atish Patra
,
15:13
Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Anup Patel
,
08:01
Re: [PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store
,
Alistair Francis
,
05:57
Re: [PATCH 2/2] target/riscv: Add short-isa-string option
,
Alistair Francis
,
05:52
Re: [PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store
,
Alistair Francis
,
05:39
Re: [PATCH 3/4] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
,
Alistair Francis
,
05:37
Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Alistair Francis
,
05:24
[PATCH] MAINTAINERS: Add myself as hw/core/uboot_image.h maintainer
,
Alistair Francis
,
05:14
May 06, 2022
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Kumar Patra
,
16:30
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Peter Maydell
,
07:00
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Daniel P . Berrangé
,
04:16
[PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store
,
~eopxd
,
01:15
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Anup Patel
,
00:01
May 05, 2022
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Kumar Patra
,
18:19
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Kumar Patra
,
17:29
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
16:35
Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Anup Patel
,
06:36
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Daniel P . Berrangé
,
06:04
Re: [PATCH 2/4] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
,
Alistair Francis
,
05:51
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Alistair Francis
,
05:37
Re: [PATCH v7 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
02:59
May 04, 2022
Re: [PATCH v7 08/12] target/riscv: Add sscofpmf extension support
,
Alistair Francis
,
06:06
Re: [PATCH v7 08/12] target/riscv: Add sscofpmf extension support
,
Alistair Francis
,
06:03
Re: [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string
,
Alistair Francis
,
05:59
Re: [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Frank Chang
,
05:54
Re: [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Alistair Francis
,
05:14
Re: [PATCH 1/3] target/riscv: Don't force update priv spec version to latest
,
Alistair Francis
,
05:14
May 03, 2022
Re: Modelling core local interrupts
,
Frank Chang
,
11:48
Re: [RFC 0/3] Introduce a new Qemu machine for RISC-V
,
Atish Patra
,
03:22
[PATCH qemu v14 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
03:14
[PATCH qemu v14 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
03:14
[PATCH qemu v14 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
03:14
[PATCH qemu v14 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
03:14
[PATCH qemu v14 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
03:14
[PATCH qemu v14 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
03:14
[PATCH qemu v14 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
03:14
[PATCH qemu v14 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
03:14
[PATCH qemu v14 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
03:14
[PATCH qemu v14 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
03:14
[PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
03:14
[PATCH qemu v14 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
03:14
[PATCH qemu v14 02/15] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
03:13
[PATCH qemu v14 00/15] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
03:13
[PATCH qemu v14 03/15] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
03:13
[PATCH qemu v14 04/15] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
03:13
May 02, 2022
[PATCH qemu v13 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
07:13
[PATCH qemu v13 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
07:12
[PATCH qemu v13 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
07:12
[PATCH qemu v13 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
07:12
[PATCH qemu v13 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
07:12
[PATCH qemu v13 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
07:12
[PATCH qemu v13 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
07:12
[PATCH qemu v13 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
07:12
[PATCH qemu v13 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
07:12
[PATCH qemu v13 03/15] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
07:12
[PATCH qemu v13 02/15] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
07:12
[PATCH qemu v13 04/15] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
07:12
[PATCH qemu v13 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
07:12
[PATCH qemu v13 00/15] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
07:12
[PATCH qemu v13 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
07:12
[PATCH qemu v13 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
07:12
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