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qemu-riscv (date)
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Last Modified: Thu Mar 31 2022 22:01:40 -0400
Messages in reverse chronological order
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March 31, 2022
[PATCH v2] target/riscv: Call probe_write() before atomic operations
,
Alistair Francis
,
22:01
Re: [PATCH] hw/riscv: Enable TPM backends
,
Bin Meng
,
20:58
[PATCH] hw/riscv: Enable TPM backends
,
Alistair Francis
,
20:19
Re: [PATCH] target/riscv: Avoid leaking "no translation" TLB entries
,
Alistair Francis
,
18:13
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Palmer Dabbelt
,
15:54
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Alistair Francis
,
01:14
Re: [PATCH] target/riscv: Avoid leaking "no translation" TLB entries
,
Alistair Francis
,
01:01
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Palmer Dabbelt
,
00:37
March 30, 2022
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Alistair Francis
,
23:23
Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions
,
Alistair Francis
,
23:19
Re: [RFC PATCH v3 1/4] target/riscv: Add smstateen support
,
Alistair Francis
,
22:43
Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions
,
Weiwei Li
,
21:24
Re: [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
,
Alistair Francis
,
20:16
Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions
,
Alistair Francis
,
20:12
Re: [PATCH v7] target/riscv: Add isa extenstion strings to the device tree
,
Alistair Francis
,
20:07
[PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
20:02
[PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
20:02
[PATCH v7 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
20:02
[PATCH v7 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
20:01
[PATCH v7 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
20:01
[PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
20:01
[PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
20:01
[PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
20:01
[PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
20:01
[PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
20:01
[PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
20:01
[PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
20:01
[PATCH v7 00/12] Improve PMU support
,
Atish Patra
,
20:01
Re: [PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
15:43
Re: [PATCH v6 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
15:42
Re: [PATCH v6 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
15:41
[PATCH] target/riscv: Avoid leaking "no translation" TLB entries
,
Palmer Dabbelt
,
13:10
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Idan Horowitz
,
13:10
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Palmer Dabbelt
,
13:06
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Palmer Dabbelt
,
12:11
Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
Weiwei Li
,
11:14
Re: Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
phantom
,
08:58
[RFC PATCH 12/18] hw/riscv/virt: prepare riscv_hart transition to cpus
,
Damien Hedde
,
08:57
[RFC PATCH 18/18] add myself as reviewer of the newly added _cpus_
,
Damien Hedde
,
08:57
[RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update
,
Damien Hedde
,
08:57
[RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class
,
Damien Hedde
,
08:57
[RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features
,
Damien Hedde
,
08:57
[RFC PATCH 15/18] hw/riscv/sifive_uµchip_pfsoc: apply riscv_hart_array update
,
Damien Hedde
,
08:57
[RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus
,
Damien Hedde
,
08:57
[RFC PATCH 13/18] hw/riscv/spike: prepare riscv_hart transition to cpus
,
Damien Hedde
,
08:57
[RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus
,
Damien Hedde
,
08:57
[RFC PATCH 07/18] hw/cpu/cpus: add a common start-powered-off property
,
Damien Hedde
,
08:57
[RFC PATCH 08/18] hw/arm/arm_cpus: add arm_cpus device
,
Damien Hedde
,
08:57
[RFC PATCH 09/18] hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus
,
Damien Hedde
,
08:57
[RFC PATCH 06/18] hw/cpu/cluster: remove cluster_id now that gdbstub is updated
,
Damien Hedde
,
08:57
[RFC PATCH 05/18] gdbstub: deal with _cpus_ object instead of _cpu-cluster_
,
Damien Hedde
,
08:57
[RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_
,
Damien Hedde
,
08:57
[RFC PATCH 00/18] user-creatable cpu clusters
,
Damien Hedde
,
08:57
[RFC PATCH 02/18] hw/cpu/cpus: introduce _cpus_ device
,
Damien Hedde
,
08:57
[RFC PATCH 03/18] hw/cpu/cpus: prepare to handle cpu clusters
,
Damien Hedde
,
08:57
[RFC PATCH 01/18] define MAX_CLUSTERS in cpu.h instead of cluster.h
,
Damien Hedde
,
08:57
Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions
,
Weiwei Li
,
08:47
[PATCH qemu v7 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
06:26
[PATCH qemu v7 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
06:26
[PATCH qemu v7 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
06:26
[PATCH qemu v7 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
06:26
[PATCH qemu v7 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
06:26
[PATCH qemu v7 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
06:25
[PATCH qemu v7 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
06:25
[PATCH qemu v7 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
06:25
[PATCH qemu v7 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
06:25
[PATCH qemu v7 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
06:25
[PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
06:25
[PATCH qemu v7 02/14] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
06:25
[PATCH qemu v7 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
06:24
[PATCH qemu v7 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
06:24
[PATCH qemu v7 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
06:24
Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
eop Chen
,
06:03
Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
Weiwei Li
,
04:28
[PATCH qemu v6 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
04:06
[PATCH qemu v6 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
04:06
[PATCH qemu v6 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
04:06
[PATCH qemu v6 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
04:06
[PATCH qemu v6 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
04:06
[PATCH qemu v6 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
04:06
[PATCH qemu v6 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
04:06
[PATCH qemu v6 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
04:06
[PATCH qemu v6 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
04:06
[PATCH qemu v6 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
04:06
[PATCH qemu v6 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
04:06
[PATCH qemu v6 02/14] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
04:06
[PATCH qemu v6 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
04:06
[PATCH qemu v6 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
04:06
[PATCH qemu v6 00/14] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
04:06
Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Alistair Francis
,
03:50
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Idan Horowitz
,
03:43
Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
陳約廷
,
03:42
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Atish Patra
,
03:36
Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Frédéric Pétrot
,
02:44
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Alistair Francis
,
02:16
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Idan Horowitz
,
02:15
Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Alistair Francis
,
01:27
March 29, 2022
[RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
,
Weiwei Li
,
22:13
[PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
,
Weiwei Li
,
22:11
Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
22:08
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Atish Patra
,
19:16
[PATCH v7] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
15:57
Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Frédéric Pétrot
,
12:29
March 28, 2022
[RFC PATCH v3 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
13:23
[RFC PATCH v3 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
13:23
[RFC PATCH v3 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
13:23
[RFC PATCH v3 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
13:23
[RFC PATCH v3 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
13:23
[PATCH v2 1/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
09:11
[PATCH v2 0/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
09:11
Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
09:10
Re: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
09:09
Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
Weiwei Li
,
07:56
Re: [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
Weiwei Li
,
07:23
[PATCH qemu v5 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
03:21
[PATCH qemu v5 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
03:21
[PATCH qemu v5 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
03:21
[PATCH qemu v5 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
03:21
[PATCH qemu v5 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
03:21
[PATCH qemu v5 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
03:21
[PATCH qemu v5 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
03:21
[PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
03:21
[PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
03:20
[PATCH qemu v5 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
03:20
[PATCH qemu v5 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
03:20
[PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
03:20
[PATCH qemu v5 02/14] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
03:20
[PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
03:20
[PATCH qemu v5 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
03:20
Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
,
Alistair Francis
,
00:01
March 27, 2022
Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix
,
Frank Chang
,
21:36
Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
,
Alistair Francis
,
21:12
Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
,
Alistair Francis
,
21:11
Re: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix
,
Alistair Francis
,
19:30
Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix
,
Alistair Francis
,
19:29
March 26, 2022
[PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
01:02
[PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix
,
Tsukasa OI
,
01:02
March 25, 2022
Re: [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
Weiwei Li
,
06:51
Re: [PATCH qemu v4 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
Weiwei Li
,
06:47
Re: [PATCH qemu v4 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
Weiwei Li
,
06:42
Re: [PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
Weiwei Li
,
06:38
Re: [PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
Weiwei Li
,
06:32
Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
,
Frank Chang
,
05:27
Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
,
Frank Chang
,
05:26
Re: [PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
Weiwei Li
,
05:10
[PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
,
Weiwei Li
,
05:00
[PATCH 1/2] target/riscv: optimize condition assign for scale < 0
,
Weiwei Li
,
05:00
Re: [PATCH 28/32] Move CPU softfloat unions to cpu-float.h
,
Juan Quintela
,
04:17
March 24, 2022
[PATCH qemu v4 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
15:04
[PATCH qemu v4 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
15:03
[PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
15:03
[PATCH qemu v4 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
15:03
[PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
15:03
[PATCH qemu v4 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
15:03
[PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
15:03
[PATCH qemu v4 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
15:03
[PATCH qemu v4 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
15:03
[PATCH qemu v4 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
15:03
[PATCH qemu v4 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
15:03
[PATCH qemu v4 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
15:03
[PATCH qemu v4 00/14] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
15:03
[PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
15:03
[PATCH qemu v4 02/14] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
15:03
Re: [RFC PATCH v2 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
04:47
Re: [RFC PATCH v2 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
04:29
Re: [RFC PATCH v2 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
04:27
March 23, 2022
Re: [PATCH v9 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Alistair Francis
,
22:54
Re: [PATCH v9 11/14] target/riscv: rvk: add support for zksed/zksh extension
,
Alistair Francis
,
22:49
[PATCH 32/32] Remove qemu-common.h include from most units
,
marcandre . lureau
,
12:02
[PATCH 28/32] Move CPU softfloat unions to cpu-float.h
,
marcandre . lureau
,
12:01
[PATCH 06/32] Replace config-time define HOST_WORDS_BIGENDIAN
,
marcandre . lureau
,
11:58
Re: [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
Weiwei Li
,
09:58
Re: [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
陳約廷
,
09:40
Re: [RFC PATCH v2 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Weiwei Li
,
09:13
Re: [RFC PATCH v2 1/4] target/riscv: Add smstateen support
,
Weiwei Li
,
09:02
Re: [RFC PATCH v2 2/4] target/riscv: smstateen check for h/senvcfg
,
Weiwei Li
,
08:52
[RFC PATCH v2 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
07:14
[RFC PATCH v2 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
07:13
[RFC PATCH v2 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
07:13
[RFC PATCH v2 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
07:13
[RFC PATCH v2 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
07:13
Re: [PATCH qemu v3 00/14] Add tail agnostic behavior for rvv instructions
,
Weiwei Li
,
03:54
Re: [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
Weiwei Li
,
03:28
Re: [PATCH qemu v3 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
Weiwei Li
,
03:14
March 22, 2022
[PATCH qemu v3 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
23:59
[PATCH qemu v3 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
23:58
[PATCH qemu v3 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
23:58
[PATCH qemu v3 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
23:58
[PATCH qemu v3 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
23:58
[PATCH qemu v3 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
23:58
[PATCH qemu v3 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
23:58
[PATCH qemu v3 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
23:58
[PATCH qemu v3 02/14] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
23:58
[PATCH qemu v3 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
23:58
[PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
23:58
[PATCH qemu v3 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
23:58
[PATCH qemu v3 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
23:58
[PATCH qemu v3 00/14] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
23:58
[PATCH qemu v3 03/14] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
23:58
[PATCH qemu v2 10/13] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
23:09
[PATCH qemu v2 09/13] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
23:09
[PATCH qemu v2 13/13] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
23:09
[PATCH qemu v2 12/13] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
23:09
[PATCH qemu v2 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
23:09
[PATCH qemu v2 08/13] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
23:09
[PATCH qemu v2 11/13] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
23:09
[PATCH qemu v2 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
23:09
[PATCH qemu v2 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
23:09
[PATCH qemu v2 03/13] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
23:09
[PATCH qemu v2 04/13] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
23:09
[PATCH qemu v2 02/13] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
23:09
[PATCH qemu v2 01/13] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
23:08
[PATCH qemu v2 00/13] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
23:08
[RFC PATCH v1 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
09:42
[RFC PATCH v1 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
09:42
[RFC PATCH v1 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
09:42
[RFC PATCH v1 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
09:42
[RFC PATCH v1 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
09:42
March 21, 2022
Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions
,
eop Chen
,
09:18
Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions
,
Weiwei Li
,
07:34
Re: [PATCH v9 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
,
Alistair Francis
,
02:06
March 20, 2022
Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
,
Alistair Francis
,
20:21
Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
,
Alistair Francis
,
19:48
Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl
,
Weiwei Li
,
00:59
March 19, 2022
Re: [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
Weiwei Li
,
22:50
Re: [PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
Weiwei Li
,
22:37
Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions
,
Weiwei Li
,
10:45
Re: [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
Weiwei Li
,
10:29
Re: [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
Weiwei Li
,
10:14
Re: [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions
,
Weiwei Li
,
10:08
Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl
,
Weiwei Li
,
09:56
[PATCH qemu 09/13] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
08:51
[PATCH qemu 13/13] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
08:51
[PATCH qemu 12/13] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
08:51
[PATCH qemu 11/13] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
08:51
[PATCH qemu 08/13] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
08:51
[PATCH qemu 02/13] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
08:51
[PATCH qemu 10/13] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
08:51
[PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
08:51
[PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
08:51
[PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
08:51
[PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
08:51
[PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
08:51
[PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
08:51
[PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
08:51
March 18, 2022
[PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
,
~eopxd
,
16:57
Re: [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
,
Alistair Francis
,
03:39
[PATCH v9 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
00:28
[PATCH v9 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
00:28
[PATCH v9 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Weiwei Li
,
00:28
[PATCH v9 12/14] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
00:20
[PATCH v9 11/14] target/riscv: rvk: add support for zksed/zksh extension
,
Weiwei Li
,
00:20
[PATCH v9 04/14] target/riscv: rvk: add support for zbkx extension
,
Weiwei Li
,
00:20
[PATCH v9 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
,
Weiwei Li
,
00:20
[PATCH v9 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
,
Weiwei Li
,
00:20
[PATCH v9 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
,
Weiwei Li
,
00:20
[PATCH v9 02/14] target/riscv: rvk: add support for zbkb extension
,
Weiwei Li
,
00:20
[PATCH v9 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
,
Weiwei Li
,
00:20
[PATCH v9 05/14] crypto: move sm4_sbox from target/arm
,
Weiwei Li
,
00:20
[PATCH v9 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
00:20
[PATCH v9 03/14] target/riscv: rvk: add support for zbkc extension
,
Weiwei Li
,
00:20
[PATCH v9 00/14] support subsets of scalar crypto extension
,
Weiwei Li
,
00:20
March 17, 2022
Re: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature
,
Alistair Francis
,
22:17
Re: [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write
,
Alistair Francis
,
22:15
Re: [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension
,
Alistair Francis
,
22:12
[PATCH v3] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
22:07
Re: [PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
19:14
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Cédric Le Goater
,
07:31
Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
06:50
Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
05:57
Re: [PATCH v6 08/12] target/riscv: Add sscofpmf extension support
,
Frank Chang
,
03:38
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
03:37
[PATCH v3 2/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
02:19
[PATCH v3 1/2] target/riscv: cpu: Fixup indentation
,
Alistair Francis
,
02:19
[PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
02:19
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Alistair Francis
,
00:40
March 16, 2022
Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
,
Bin Meng
,
23:57
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
22:11
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Alistair Francis
,
18:35
[PATCH v6] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
13:58
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
phantom
,
13:23
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
11:13
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Philippe Mathieu-Daudé
,
09:12
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Marc-André Lureau
,
09:09
Re: [PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Bin Meng
,
09:07
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Philippe Mathieu-Daudé
,
09:04
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Halil Pasic
,
07:37
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Thomas Huth
,
07:23
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Marc-André Lureau
,
07:21
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Halil Pasic
,
07:16
Re: [PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
Thomas Huth
,
06:29
[PATCH 10/27] Replace config-time define HOST_WORDS_BIGENDIAN
,
marcandre . lureau
,
05:53
Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions
,
Anup Patel
,
04:00
Re: [PATCH v2 1/2] target/riscv: cpu: Fixup indentation
,
Richard Henderson
,
02:15
Re: [PATCH v2 2/2] target/riscv: Allow software access to MIP SEIP
,
Richard Henderson
,
02:13
March 15, 2022
[PATCH v2 2/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
21:59
[PATCH v2 1/2] target/riscv: cpu: Fixup indentation
,
Alistair Francis
,
21:59
[PATCH v2 0/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
21:59
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Alistair Francis
,
19:43
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Alistair Francis
,
18:53
[PATCH] target/riscv: Exit current TB after an sfence.vma
,
Idan Horowitz
,
15:42
Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
,
Richard Henderson
,
15:37
Re: [PATCH v5] target/riscv: Add isa extenstion strings to the device tree
,
Atish Kumar Patra
,
14:21
Re: [PATCH 1/2] target/riscv: cpu: Fixup indentation
,
Weiwei Li
,
11:00
Re: [PATCH v6 10/12] target/riscv: Add few cache related PMU events
,
Frank Chang
,
05:25
Re: [PATCH v5] target/riscv: Add isa extenstion strings to the device tree
,
Bin Meng
,
05:17
Re: [PATCH 2/2] target/riscv: Allow software access to MIP SEIP
,
Bin Meng
,
04:58
Re: [PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Frank Chang
,
03:41
Re: [PATCH 1/2] target/riscv: cpu: Fixup indentation
,
Bin Meng
,
03:29
[PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
02:56
[PATCH v4 6/7] target/riscv: cpu: Enable native debug feature
,
Bin Meng
,
02:56
[PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
02:56
[PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
02:55
[PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
02:55
[PATCH v4 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
02:55
[PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension
,
Bin Meng
,
02:55
[PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
,
Bin Meng
,
02:55
[PATCH 0/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
02:40
[PATCH 1/2] target/riscv: cpu: Fixup indentation
,
Alistair Francis
,
02:40
[PATCH 2/2] target/riscv: Allow software access to MIP SEIP
,
Alistair Francis
,
02:40
March 14, 2022
[PATCH v5] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
19:43
Re: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
05:44
Re: [RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
05:26
March 11, 2022
[PATCH v2] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
04:46
Re: [PATCH] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
03:39
Re: [PATCH] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Alistair Francis
,
02:54
Re: [PATCH v8 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Alistair Francis
,
02:14
Re: [PATCH v8 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
,
Alistair Francis
,
02:09
March 10, 2022
Re: [PATCH] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
23:58
Re: [PATCH v8 04/14] target/riscv: rvk: add support for zbkx extension
,
Alistair Francis
,
22:09
Re: [PATCH] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Alistair Francis
,
21:58
Re: [PATCH v8 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
,
Alistair Francis
,
21:26
Re: [PATCH v8 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
,
Alistair Francis
,
21:22
Re: [PATCH v4] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
19:46
Re: [PATCH v4] target/riscv: Add isa extenstion strings to the device tree
,
Atish Kumar Patra
,
13:42
Re: [PATCH v2] tests: add (riscv virt) machine mapping to testenv
,
laokz
,
01:06
March 09, 2022
Re: [PATCH v2] tests: add (riscv virt) machine mapping to testenv
,
Hanna Reitz
,
09:56
Re: [PATCH 1/1] target/riscv: misa to ISA string conversion fix
,
Frank Chang
,
09:09
Re: [PATCH v4] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
08:47
March 08, 2022
[PATCH v4] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
19:53
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
17:59
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
17:56
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
17:52
Re: [RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp
,
Atish Patra
,
17:43
Re: [RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp
,
Alistair Francis
,
16:32
Re: [PATCH v2] tests: add (riscv virt) machine mapping to testenv
,
Alistair Francis
,
01:41
March 07, 2022
[PATCH v2] tests: add (riscv virt) machine mapping to testenv
,
laokz
,
23:34
Re: [PATCH] tests: add (riscv virt) machine mapping to testenv
,
Hanna Reitz
,
13:17
[PATCH] tests: add (riscv virt) machine mapping to testenv
,
laokz
,
09:30
Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions
,
Frank Chang
,
02:31
March 06, 2022
Re: [PATCH v5 0/6] Privilege version update
,
Alistair Francis
,
21:15
Re: [PATCH v5 0/6] Privilege version update
,
Alistair Francis
,
21:14
Re: [PATCH v3 2/2] riscv: opentitan: Connect opentitan SPI Host
,
Alistair Francis
,
21:10
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
01:47
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
01:43
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Kumar Patra
,
01:12
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Anup Patel
,
00:51
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Frank Chang
,
00:36
March 05, 2022
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Kumar Patra
,
18:42
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Heiko Stuebner
,
12:26
March 04, 2022
Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e devices
,
Philippe Mathieu-Daudé
,
09:50
March 03, 2022
Re: [RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp
,
Anup Patel
,
23:05
[RFC PATCH 3/3] target/riscv: Add vstimecmp support
,
Atish Patra
,
22:20
[RFC PATCH 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
22:20
[RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp
,
Atish Patra
,
22:20
[RFC PATCH 0/3] Implement Sstc extension
,
Atish Patra
,
22:20
[PATCH v6 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
18:55
[PATCH v6 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
18:55
[PATCH v6 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
18:55
[PATCH v6 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
18:55
[PATCH v6 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
18:55
[PATCH v6 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
18:55
[PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
18:55
[PATCH v6 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
18:55
[PATCH v6 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
18:54
[PATCH v6 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
18:54
[PATCH v6 03/12] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
18:54
[PATCH v6 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
18:54
[PATCH v6 00/12] Improve PMU support
,
Atish Patra
,
18:54
Re: [PATCH] docs/system: riscv: Update description of CPU
,
Palmer Dabbelt
,
15:55
Re: [PATCH v5 08/12] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
15:16
Re: [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Kumar Patra
,
15:04
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
,
Atish Patra
,
14:04
Re: [PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
13:55
[PATCH v5 6/6] target/riscv: Enable privileged spec version 1.12
,
Atish Patra
,
13:55
[PATCH v5 5/6] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
13:55
[PATCH v5 4/6] target/riscv: Add support for mconfigptr
,
Atish Patra
,
13:55
[PATCH v5 3/6] target/riscv: Introduce privilege version field in the CSR ops.
,
Atish Patra
,
13:54
[PATCH v5 2/6] target/riscv: Add the privileged spec version 1.12.0
,
Atish Patra
,
13:54
[PATCH v5 1/6] target/riscv: Define simpler privileged spec version numbering
,
Atish Patra
,
13:54
[PATCH v5 0/6] Privilege version update
,
Atish Patra
,
13:54
Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Kumar Patra
,
05:03
Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function
,
Alistair Francis
,
00:23
March 02, 2022
[PATCH v3 2/2] riscv: opentitan: Connect opentitan SPI Host
,
Alistair Francis
,
23:55
[PATCH v3 1/2] hw/ssi: Add Ibex SPI device model
,
Alistair Francis
,
23:55
Re: [PATCH v5 00/12] Improve PMU support
,
Alistair Francis
,
22:21
Re: [PATCH v5 10/12] target/riscv: Add few cache related PMU events
,
Alistair Francis
,
18:36
Re: [PATCH v5 09/12] target/riscv: Simplify counter predicate function
,
Alistair Francis
,
17:45
Re: [PATCH v5 08/12] target/riscv: Add sscofpmf extension support
,
Alistair Francis
,
17:37
[PATCH] target/riscv: write back unmodified value for csrrc/csrrs with rs1 is not x0 but holding zero
,
Weiwei Li
,
07:30
Re: [PATCH v4 1/2] accel/tcg: Add probe_access_range_flags interface
,
Alistair Francis
,
03:01
March 01, 2022
Re: [PATCH RESEND 2/2] hw/riscv/sifive_u: Resolve redundant property accessors
,
Alistair Francis
,
23:42
Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
19:57
[PATCH RESEND 2/2] hw/riscv/sifive_u: Resolve redundant property accessors
,
Bernhard Beschow
,
17:52
Re: [PATCH v8 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Richard Henderson
,
13:24
Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
,
Richard Henderson
,
10:59
[PATCH v8 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
,
Weiwei Li
,
07:05
[PATCH v8 11/14] target/riscv: rvk: add support for zksed/zksh extension
,
Weiwei Li
,
07:05
[PATCH v8 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
07:01
[PATCH v8 12/14] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
07:01
[PATCH v8 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Weiwei Li
,
07:01
[PATCH v8 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
,
Weiwei Li
,
07:01
[PATCH v8 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
07:01
[PATCH v8 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
,
Weiwei Li
,
07:00
[PATCH v8 03/14] target/riscv: rvk: add support for zbkc extension
,
Weiwei Li
,
07:00
[PATCH v8 02/14] target/riscv: rvk: add support for zbkb extension
,
Weiwei Li
,
07:00
[PATCH v8 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
07:00
[PATCH v8 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
,
Weiwei Li
,
07:00
[PATCH v8 05/14] crypto: move sm4_sbox from target/arm
,
Weiwei Li
,
07:00
[PATCH v8 04/14] target/riscv: rvk: add support for zbkx extension
,
Weiwei Li
,
07:00
[PATCH v8 00/14] support subsets of scalar crypto extension
,
Weiwei Li
,
07:00
Re: [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation
,
Alistair Francis
,
01:14
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