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qemu-riscv (date)
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Last Modified: Wed Jun 30 2021 23:07:56 -0400
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June 30, 2021
Re: [PATCH v3 00/37] target/riscv: support packed extension v0.9.4
,
LIU Zhiwei
,
23:07
Re: [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions
,
Alistair Francis
,
22:08
Re: [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
,
Alistair Francis
,
22:03
Re: [PATCH v3 00/37] target/riscv: support packed extension v0.9.4
,
Alistair Francis
,
21:30
Re: [PATCH] target/riscv: pmp: Fix some typos
,
Alistair Francis
,
21:27
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
01:37
June 28, 2021
Re: [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode
,
LIU Zhiwei
,
22:55
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
22:54
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
22:51
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
22:45
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
17:40
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
10:30
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
08:58
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
06:50
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
06:26
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
06:17
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
05:11
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
04:45
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
04:19
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
04:12
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
04:08
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
04:03
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
03:49
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
03:40
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
03:23
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
03:17
June 27, 2021
Re: [PATCH] target/riscv: pmp: Fix some typos
,
Alistair Francis
,
20:22
Re: [PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc
,
Alistair Francis
,
20:21
Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
,
Frank Chang
,
11:55
Re: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode
,
Frank Chang
,
11:39
Re: [PATCH] target/riscv: pmp: Fix some typos
,
Philippe Mathieu-Daudé
,
11:34
[PATCH 2/2] docs/system: riscv: Add documentation for virt machine
,
Bin Meng
,
10:28
[PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc
,
Bin Meng
,
10:28
Re: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
,
Frank Chang
,
08:08
[PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Bin Meng
,
08:06
[PATCH] target/riscv: pmp: Fix some typos
,
Bin Meng
,
07:57
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Frank Chang
,
06:07
Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
,
Frank Chang
,
04:59
Re: [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode
,
Frank Chang
,
04:33
Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
,
Frank Chang
,
04:23
Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
,
Frank Chang
,
02:51
Re: [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode
,
Frank Chang
,
02:45
June 26, 2021
Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
,
Frank Chang
,
13:24
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
13:20
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
13:16
Re: [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode
,
Frank Chang
,
11:32
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
11:27
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
11:20
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
11:03
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
08:56
June 24, 2021
Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
,
Jose Martins
,
09:48
Re: [PATCH v3 00/37] target/riscv: support packed extension v0.9.4
,
no-reply
,
07:55
[PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line
,
LIU Zhiwei
,
07:15
[PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
,
LIU Zhiwei
,
07:14
[PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
07:14
[PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
,
LIU Zhiwei
,
07:13
[PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
,
LIU Zhiwei
,
07:13
[PATCH v3 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions
,
LIU Zhiwei
,
07:13
[PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
,
LIU Zhiwei
,
07:12
[PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
,
LIU Zhiwei
,
07:12
[PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
07:11
[PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:11
[PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
07:10
[PATCH v3 26/37] target/riscv: 32-bit Computation Instructions
,
LIU Zhiwei
,
07:10
[PATCH v3 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions
,
LIU Zhiwei
,
07:09
[PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
,
LIU Zhiwei
,
07:09
[PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:08
[PATCH v3 22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:07
[PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:07
[PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
,
LIU Zhiwei
,
07:06
[PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
07:06
[PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:05
[PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
07:05
[PATCH v3 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions
,
LIU Zhiwei
,
07:04
[PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
,
LIU Zhiwei
,
07:04
[PATCH v3 14/37] target/riscv: 16-bit Packing Instructions
,
LIU Zhiwei
,
07:03
[PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions
,
LIU Zhiwei
,
07:03
[PATCH v3 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions
,
LIU Zhiwei
,
07:02
[PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
,
LIU Zhiwei
,
07:02
[PATCH v3 10/37] target/riscv: SIMD 8-bit Multiply Instructions
,
LIU Zhiwei
,
07:01
[PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions
,
LIU Zhiwei
,
07:01
[PATCH v3 08/37] target/riscv: SIMD 8-bit Compare Instructions
,
LIU Zhiwei
,
07:00
[PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions
,
LIU Zhiwei
,
07:00
[PATCH v3 06/37] target/riscv: SIMD 8-bit Shift Instructions
,
LIU Zhiwei
,
06:59
[PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions
,
LIU Zhiwei
,
06:59
[PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
,
LIU Zhiwei
,
06:58
[PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
,
LIU Zhiwei
,
06:58
[PATCH v3 02/37] target/riscv: Make the vector helper functions public
,
LIU Zhiwei
,
06:57
[PATCH v3 01/37] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
06:57
[PATCH v3 00/37] target/riscv: support packed extension v0.9.4
,
LIU Zhiwei
,
06:56
Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
,
LIU Zhiwei
,
02:07
June 21, 2021
Re: [PATCH v3 0/3] OpenTitan: Add support for the RISC-V timer
,
Alistair Francis
,
18:39
Re: [PATCH 18/26] target/riscv: Use translator_use_goto_tb
,
Alistair Francis
,
18:23
[PATCH v1 1/5] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
11:21
June 20, 2021
[PATCH 18/26] target/riscv: Use translator_use_goto_tb
,
Richard Henderson
,
21:35
June 18, 2021
Re: [PATCH v16 93/99] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
12:34
Re: [PATCH v3 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
05:59
[PATCH v3 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
,
Alistair Francis
,
03:28
[PATCH v3 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
03:28
[PATCH v3 1/3] hw/char/ibex_uart: Make the register layout private
,
Alistair Francis
,
03:28
[PATCH v3 0/3] OpenTitan: Add support for the RISC-V timer
,
Alistair Francis
,
03:27
Re: [PATCH v5 2/2] hw/char: QOMify sifive_uart
,
Alistair Francis
,
03:23
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
03:03
Re: [PATCH v5 2/2] hw/char: QOMify sifive_uart
,
Alistair Francis
,
02:52
Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Alistair Francis
,
02:50
Re: [PATCH] target/riscv: gdbstub: Fix dynamic CSR XML generation
,
Alistair Francis
,
02:39
June 17, 2021
Re: [PATCH 16/21] linux-user/riscv: Implement setup_sigtramp
,
Alistair Francis
,
21:30
June 16, 2021
Re: [PATCH 16/21] linux-user/riscv: Implement setup_sigtramp
,
Philippe Mathieu-Daudé
,
12:50
[PATCH v5 2/2] hw/char: QOMify sifive_uart
,
Lukas Jünger
,
05:23
[PATCH v5 1/2] hw/char: Consistent function names for sifive_uart
,
Lukas Jünger
,
05:23
[PATCH v5 0/2] QOMify Sifive UART Model
,
Lukas Jünger
,
05:23
Re: [PATCH v4 2/2] hw/char: QOMify sifive_uart
,
Bin Meng
,
05:16
Re: [PATCH v4 1/2] hw/char: Consistent function names for sifive_uart
,
Bin Meng
,
05:15
Re: [PATCH v4 1/2] hw/char: Consistent function names for sifive_uart
,
Alistair Francis
,
02:55
[PATCH v4 1/2] hw/char: Consistent function names for sifive_uart
,
Lukas Jünger
,
02:43
[PATCH v4 2/2] hw/char: QOMify sifive_uart
,
Lukas Jünger
,
02:43
[PATCH v4 0/2] QOMify Sifive UART Model
,
Lukas Jünger
,
02:43
June 15, 2021
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
LIU Zhiwei
,
22:56
[PATCH 16/21] linux-user/riscv: Implement setup_sigtramp
,
Richard Henderson
,
21:12
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Anup Patel
,
08:49
Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Alistair Francis
,
06:43
Re: [PATCH] target/riscv: gdbstub: Fix dynamic CSR XML generation
,
Alistair Francis
,
06:42
Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
,
Bin Meng
,
05:07
[PATCH] target/riscv: gdbstub: Fix dynamic CSR XML generation
,
Bin Meng
,
04:51
Re: [PATCH v3 2/2] hw/char: sifive_uart
,
Alistair Francis
,
04:17
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Alistair Francis
,
04:11
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Alistair Francis
,
03:46
June 14, 2021
Re: [PATCH v3 1/2] hw/char: sifive_uart
,
Bin Meng
,
22:23
Re: [PATCH v3 1/2] hw/char: sifive_uart
,
Bin Meng
,
22:19
Re: [PATCH v2 00/37] target/riscv: support packed extension v0.9.4
,
no-reply
,
18:56
Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Bin Meng
,
08:23
Re: [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
,
Bin Meng
,
08:23
Re: [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Bin Meng
,
08:22
June 13, 2021
Re: [PATCH v3 1/2] hw/char: sifive_uart
,
Alistair Francis
,
22:14
[PATCH v3 2/2] hw/char: sifive_uart
,
Lukas Jünger
,
10:12
[PATCH v3 1/2] hw/char: sifive_uart
,
Lukas Jünger
,
10:12
[PATCH v3 0/2] QOMify Sifive UART Model
,
Lukas Jünger
,
10:12
Re: [RFC PATCH 03/11] hw/intc: Add CLIC device
,
Frank Chang
,
06:11
June 12, 2021
[PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
,
Anup Patel
,
12:07
[PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
,
Anup Patel
,
12:06
[PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
,
Anup Patel
,
12:06
[PATCH v1 0/3] RISC-V ACLINT Support
,
Anup Patel
,
12:06
June 11, 2021
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Anup Patel
,
10:04
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Paolo Bonzini
,
07:52
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
LIU Zhiwei
,
05:26
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Frank Chang
,
05:08
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
LIU Zhiwei
,
04:57
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Alistair Francis
,
04:46
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Frank Chang
,
04:42
Re: [PATCH 0/4] AIA local interrupt CSR support
,
Alistair Francis
,
04:41
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
LIU Zhiwei
,
04:30
Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
,
Frank Chang
,
04:15
Re: [PATCH 0/4] AIA local interrupt CSR support
,
Anup Patel
,
02:47
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Anup Patel
,
01:05
Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
,
Anup Patel
,
00:58
Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
,
LIU Zhiwei
,
00:36
June 10, 2021
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
LIU Zhiwei
,
22:33
Re: [RFC PATCH v3 1/2] Adding Andes AX25 CPU model
,
Bin Meng
,
19:22
Re: [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
,
Alistair Francis
,
19:20
Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
,
Alistair Francis
,
19:19
Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
,
Alistair Francis
,
19:16
Re: [PATCH 2/2] target/riscv: remove force HS exception
,
Alistair Francis
,
19:15
Re: [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
19:14
Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
,
Alistair Francis
,
19:12
Re: [PATCH v1 1/1] target/riscv: Use target_ulong for the DisasContext misa
,
Alistair Francis
,
19:03
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
19:02
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
19:00
Re: [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
,
Alistair Francis
,
18:58
Re: [RFC PATCH v3 1/2] Adding Andes AX25 CPU model
,
Alistair Francis
,
18:50
Re: [PATCH v9 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
,
Alistair Francis
,
18:47
Re: [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
,
Alistair Francis
,
18:27
Re: [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions
,
Richard Henderson
,
15:44
Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
,
Richard Henderson
,
15:39
Re: [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
,
Richard Henderson
,
14:00
Re: [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
,
Richard Henderson
,
12:19
[RFC PATCH v3 0/2] Proposing custom CSR handling logic
,
Ruinland Chuan-Tzu Tsai
,
10:45
[RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
,
Ruinland Chuan-Tzu Tsai
,
10:45
[RFC PATCH v3 1/2] Adding Andes AX25 CPU model
,
Ruinland Chuan-Tzu Tsai
,
10:45
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
Richard Henderson
,
09:30
[PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line
,
LIU Zhiwei
,
04:18
[PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
,
LIU Zhiwei
,
04:17
[PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
04:17
[PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
,
LIU Zhiwei
,
04:16
[PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
,
LIU Zhiwei
,
04:16
[PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions
,
LIU Zhiwei
,
04:15
[PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
,
LIU Zhiwei
,
04:15
[PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
,
LIU Zhiwei
,
04:14
[PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
,
LIU Zhiwei
,
04:14
[PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:13
[PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
04:13
[PATCH v2 26/37] target/riscv: 32-bit Computation Instructions
,
LIU Zhiwei
,
04:12
[PATCH v2 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions
,
LIU Zhiwei
,
04:12
[PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
,
LIU Zhiwei
,
04:11
[PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:11
[PATCH v2 22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:10
[PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:10
[PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
,
LIU Zhiwei
,
04:09
[PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
,
LIU Zhiwei
,
04:09
[PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:08
[PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
,
LIU Zhiwei
,
04:08
[PATCH v2 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions
,
LIU Zhiwei
,
04:07
[PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
,
LIU Zhiwei
,
04:07
[PATCH v2 14/37] target/riscv: 16-bit Packing Instructions
,
LIU Zhiwei
,
04:06
[PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions
,
LIU Zhiwei
,
04:06
[PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions
,
LIU Zhiwei
,
04:05
[PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
,
LIU Zhiwei
,
04:05
[PATCH v2 10/37] target/riscv: SIMD 8-bit Multiply Instructions
,
LIU Zhiwei
,
04:04
[PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions
,
LIU Zhiwei
,
04:04
[PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions
,
LIU Zhiwei
,
04:03
[PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions
,
LIU Zhiwei
,
04:03
[PATCH v2 06/37] target/riscv: SIMD 8-bit Shift Instructions
,
LIU Zhiwei
,
04:02
[PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions
,
LIU Zhiwei
,
04:01
[PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
,
LIU Zhiwei
,
04:01
[PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
,
LIU Zhiwei
,
04:01
[PATCH v2 02/37] target/riscv: Make the vector helper functions public
,
LIU Zhiwei
,
04:00
[PATCH v2 01/37] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
03:59
[PATCH v2 00/37] target/riscv: support packed extension v0.9.4
,
LIU Zhiwei
,
03:59
June 09, 2021
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
LIU Zhiwei
,
21:43
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Paolo Bonzini
,
03:57
June 08, 2021
Re: [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
,
Bin Meng
,
21:45
Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
21:44
[PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
,
Alistair Francis
,
19:49
[PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
19:49
[PATCH v2 1/3] hw/char/ibex_uart: Make the register layout private
,
Alistair Francis
,
19:48
[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
,
Alistair Francis
,
19:48
June 07, 2021
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
Richard Henderson
,
11:59
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
Richard Henderson
,
11:53
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
LIU Zhiwei
,
05:22
Re: TCG op for 32 bit only cpu on qemu-riscv64
,
Alistair Francis
,
02:23
June 06, 2021
TCG op for 32 bit only cpu on qemu-riscv64
,
LIU Zhiwei
,
23:09
June 05, 2021
Re: [PATCH v16 93/99] meson: Introduce target-specific Kconfig
,
Richard Henderson
,
18:33
Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
,
Laurent Vivier
,
14:59
June 04, 2021
Re: [PATCH v16 13/99] meson: add target_user_arch
,
Philippe Mathieu-Daudé
,
14:01
[PATCH v16 93/99] meson: Introduce target-specific Kconfig
,
Alex Bennée
,
12:03
[PATCH v16 13/99] meson: add target_user_arch
,
Alex Bennée
,
11:53
June 03, 2021
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
22:41
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
22:38
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
22:34
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
22:33
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
22:11
Re: [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
,
Alistair Francis
,
19:23
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Alistair Francis
,
19:21
Re: [PATCH v2 00/12] hw: Various Kconfig fixes
,
Alex Bennée
,
12:41
June 02, 2021
Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
15:15
[PATCH 2/2] target/riscv: remove force HS exception
,
Jose Martins
,
15:12
[PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
15:12
[PATCH 0/2] target/riscv: fix hypervisor exceptions
,
Jose Martins
,
15:11
June 01, 2021
Re: HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit
,
Rahul Pathak
,
14:37
Re: HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit
,
Rahul Pathak
,
10:18
Re: HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit
,
Bin Meng
,
10:09
Re: [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
,
Bin Meng
,
09:10
Re: [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
,
Bin Meng
,
09:05
Re: [PATCH v1 1/3] hw/char/ibex_uart: Make the register layout private
,
Bin Meng
,
07:48
Re: [PATCH v1 1/1] target/riscv: Use target_ulong for the DisasContext misa
,
Bin Meng
,
07:46
Re: [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
,
Alistair Francis
,
02:42
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