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Re: [Qemu-trivial] [PATCH 0/1] target/arm: add data cache invalidation c

From: Michael Tokarev
Subject: Re: [Qemu-trivial] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5
Date: Tue, 23 May 2017 17:50:18 +0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0

28.04.2017 15:56, Luc MICHEL wrote:
> This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor 
> instruction
> to the cortex-r5. As stated in the TRM, this instruction invalidates all the
> data cache. This trivial patch implements it as NOP as cache operations are 
> not
> implemented in QEMU.
> The documentation is here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html

Applied to -trivial, since no one else picked it up so far :)



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