Re: [PATCH v4 1/4] target/sh4: Fix ADDV opcode

[Yoshinori Sato]

On Wed, 01 May 2024 01:31:22 +0900,
Philippe Mathieu-Daudé wrote:
> 
> The documentation says:
> 
>   ADDV Rm, Rn        Rn + Rm -> Rn, overflow -> T
> 
> But QEMU implementation was:
> 
>   ADDV Rm, Rn        Rn + Rm -> Rm, overflow -> T
> 
> Fix by filling the correct Rm register.
> 
> Add tests provided by Paul Cercueil.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG")
> Reported-by: Paul Cercueil <paul@crapouillou.net>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/translate.c        |  2 +-
>  tests/tcg/sh4/test-addv.c     | 27 +++++++++++++++++++++++++++
>  tests/tcg/sh4/Makefile.target |  3 +++
>  3 files changed, 31 insertions(+), 1 deletion(-)
>  create mode 100644 tests/tcg/sh4/test-addv.c
> 
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index ebb6c901bf..4a1dd0d1f4 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -714,7 +714,7 @@ static void _decode_opc(DisasContext * ctx)
>              tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
>              tcg_gen_andc_i32(cpu_sr_t, t1, t2);
>              tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
> -            tcg_gen_mov_i32(REG(B7_4), t0);
> +            tcg_gen_mov_i32(REG(B11_8), t0);
>          }
>          return;
>      case 0x2009: /* and Rm,Rn */
> diff --git a/tests/tcg/sh4/test-addv.c b/tests/tcg/sh4/test-addv.c
> new file mode 100644
> index 0000000000..64f709161f
> --- /dev/null
> +++ b/tests/tcg/sh4/test-addv.c
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +#include <limits.h>
> +#include <stdio.h>
> +#include <stdlib.h>
> +
> +static void addv(const int a, const int b, const int res, const int carry)
> +{
> +    int o = a, c;
> +
> +    asm volatile("addv %2,%0\n"
> +                 "movt %1\n"
> +                 : "+r"(o), "=r"(c) : "r"(b) :);
> +
> +    if (c != carry || aw != res) {
> +        printf("ADDV %d, %d = %d/%d [T = %d/%d]\n", a, b, o, res, c, carry);
> +        abort();
> +    }
> +}
> +
> +int main(void)
> +{
> +    addv(INT_MAX, 1, INT_MIN, 1);
> +    addv(INT_MAX - 1, 1, INT_MAX, 0);
> +
> +    return 0;
> +}
> diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target
> index 4d09291c0c..521b8b0a76 100644
> --- a/tests/tcg/sh4/Makefile.target
> +++ b/tests/tcg/sh4/Makefile.target
> @@ -17,3 +17,6 @@ TESTS += test-macl
>  
>  test-macw: CFLAGS += -O -g
>  TESTS += test-macw
> +
> +test-addv: CFLAGS += -O -g
> +TESTS += test-addv
> -- 
> 2.41.0
> 

Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>

-- 
Yosinori Sato