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Re: [Qemu-stable] [PATCH] piix: do not reset APIC base address (0x80) on


From: Gal Hammer
Subject: Re: [Qemu-stable] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
Date: Wed, 18 Dec 2013 17:16:29 +0200
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0

On 18/12/2013 16:19, Paolo Bonzini wrote:

The PIIX spec says that during S3 the chipset provides "Shadow registers
for standard AT write only registers to save and restore system state
information"  These are just for the 825x (DMA controller, PIC, PIT).
We do not emulate them and our BIOS does not support them.

I was told that a few memory controller registers survive S3, which in
our case would be the i440FX's PAM registers, but I don't think this
register should be one of them.

What guest is breaking and how?  Does the guest usually initialize this
register, or does the firmware (SeaBIOS) do that?  If the latter, this
could be a SeaBIOS bug instead.

Both Windows and Linux guests are breaking when system is suspend. On system wakeup nothing occurs and the OS is not restored.

I don't know the answer for the remaining questions.

Thanks,

    Gal.





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