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[Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros |
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Date: |
Sat, 25 May 2019 18:09:43 -0700 |
From: Alistair Francis <address@hidden>
Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_bits.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fe7164754b19..52c21699774f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -202,6 +202,12 @@
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH 0x7b2
+/* Hpervisor CSRs */
+#define CSR_HSTATUS 0xa00
+#define CSR_HEDELEG 0xa02
+#define CSR_HIDELEG 0xa03
+#define CSR_HGATP 0xa80
+
/* Performance Counters */
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
@@ -292,9 +298,6 @@
#define CSR_MHPMCOUNTER31H 0xb9f
/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
-#define CSR_HSTATUS 0x200
-#define CSR_HEDELEG 0x202
-#define CSR_HIDELEG 0x203
#define CSR_HIE 0x204
#define CSR_HTVEC 0x205
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25