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[Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt |
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Date: |
Tue, 19 Mar 2019 05:48:02 -0700 |
From: Bin Meng <address@hidden>
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_uart.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 456a3d3697c2..3b3f94f51ddf 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s)
static void update_irq(SiFiveUARTState *s)
{
int cond = 0;
- if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) {
+ if ((s->ie & SIFIVE_UART_IE_TXWM) ||
+ ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) {
cond = 1;
}
if (cond) {
@@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr,
switch (addr) {
case SIFIVE_UART_TXFIFO:
qemu_chr_fe_write(&s->chr, &ch, 1);
+ update_irq(s);
return;
case SIFIVE_UART_IE:
s->ie = val64;
--
2.19.2
- [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/03/19