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[Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the de
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree |
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Date: |
Tue, 19 Mar 2019 05:48:03 -0700 |
From: Bin Meng <address@hidden>
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3199238ba01e..5ecc47cea35d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -244,7 +244,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
SIFIVE_U_CLOCK_FREQ / 2);
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
--
2.19.2
- [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19