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[Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetre
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree |
Date: |
Wed, 13 Mar 2019 07:36:48 -0700 |
From: Bastian Koppelmann <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60 +++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c9840d..6319f872ac1d 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 0f837903491b..172dbfa919b6 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -377,3 +377,63 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
--
2.19.2
- [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr(), (continued)
- [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 09/29] target/riscv: Convert RV32A insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 08/29] target/riscv: Convert RVXM insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 03/29] target/riscv: Convert RV32I load/store insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 10/29] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 04/29] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 02/29] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/03/13
- [Qemu-riscv] [PULL 01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/03/13
- Re: [Qemu-riscv] [PULL] target/riscv: Convert to decodetree, Peter Maydell, 2019/03/14