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[Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G()
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G() |
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Date: |
Tue, 12 Mar 2019 06:15:26 -0700 |
From: Bastian Koppelmann <address@hidden>
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/translate.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 92be090bc7bb..049fa65c6611 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,24 +651,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(DisasContext *ctx)
-{
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
-
- switch (op) {
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -685,8 +667,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.19.2
- [Qemu-riscv] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, (continued)
- [Qemu-riscv] [PULL] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G(),
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/12