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[Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge to level |
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Date: |
Sat, 9 Feb 2019 01:00:33 +0000 |
From: Michael Clark <address@hidden>
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.
Fixes WFI doesn't return when a IPI is issued:
- https://github.com/riscv/riscv-qemu/issues/132
To test:
1) Apply RISC-V Linux CPU hotplug patch:
- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html
2) Enable CONFIG_CPU_HOTPLUG in linux .config
3) Try to offline and online cpus:
echo 1 > /sys/devices/system/cpu/cpu2/online
echo 0 > /sys/devices/system/cpu/cpu2/online
echo 1 > /sys/devices/system/cpu/cpu2/online
Reported-by: Atish Patra <address@hidden>
Cc: Atish Patra <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 555756d40c..073bdcfe74 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -95,9 +95,9 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask,
uint32_t value)
cmp = atomic_cmpxchg(&env->mip, old, new);
} while (old != cmp);
- if (new && !old) {
+ if (new) {
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else if (!new && old) {
+ } else {
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
--
2.20.1
- [Qemu-riscv] [PATCH v1 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is correctly cast, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 02/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 03/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 04/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 05/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 06/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 07/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge to level,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 09/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 10/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 11/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/08