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[Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrup
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts |
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Date: |
Wed, 26 Dec 2018 09:19:52 -0800 |
From: Alistair Francis <address@hidden>
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <address@hidden>
Tested-by: Guenter Roeck <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbfe8..2b2e6dd4ea6b 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
- VIRTIO_NDEV = 10
+ VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
enum {
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/26