Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

On Wed, Nov 21, 2018 at 10:45 AM Logan Gunthorpe <address@hidden> wrote:
>
>
>
> On 2018-11-21 11:17 a.m., Alistair Francis wrote:
> > On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe <address@hidden> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> >>> Increase the number of interrupts to match the HiFive Unleashed board.
> >>>
> >>> Signed-off-by: Alistair Francis <address@hidden>
> >>> ---
> >>>  include/hw/riscv/virt.h | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> >>> index 91163d6cbf..7cb2742070 100644
> >>> --- a/include/hw/riscv/virt.h
> >>> +++ b/include/hw/riscv/virt.h
> >>> @@ -45,7 +45,7 @@ enum {
> >>>      UART0_IRQ = 10,
> >>>      VIRTIO_IRQ = 1, /* 1 to 8 */
> >>>      VIRTIO_COUNT = 8,
> >>> -    VIRTIO_NDEV = 10
> >>> +    VIRTIO_NDEV = 0x35
> >>
> >> Why 0x35? Based on the PCI patch we are using only 36 interrupts, not 53...
> >
> > This is just for future proofing. There is no reason to set the number
> > lower then the number of interrupts we have, now hopefully this won't
> > keep churning every time we add a device.
>
> Makes sense. Still 53 is an odd number.

Agreed. It's the same number as the last interrupt in the QEMU SiFive
U machine. So that is where it came from.

Alistair

>
> Logan