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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X
From: |
Guenter Roeck |
Subject: |
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe |
Date: |
Wed, 21 Nov 2018 10:36:13 -0800 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
Hi Logan,
On Wed, Nov 21, 2018 at 11:05:21AM -0700, Logan Gunthorpe wrote:
>
>
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Connect the Xilinx PCIe device based on the information in the device
> > tree stored in the ROM of the HiFish Unleashed board.
>
> I only briefly tested this patch but could not get any PCI devices to
> come up with the sifive_u machine. Depending on the kernel I tried, it
> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> the DT) or it appears to successfully initialize a Microsemi device but
> did not enumerate any devices underneath.
What kernel configuration, devicetree, and qemu command line do you use
for the sifive_u machine ?
Thanks,
Guenter
>
> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> least explained in the commit message.
>
> Thanks,
>
> Logan
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, (continued)
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Guenter Roeck, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/26
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe,
Guenter Roeck <=
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
[Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21