Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive

qemu-riscv

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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X

From:	Logan Gunthorpe
Subject:	Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
Date:	Wed, 21 Nov 2018 11:05:21 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Connect the Xilinx PCIe device based on the information in the device
> tree stored in the ROM of the HiFish Unleashed board.

I only briefly tested this patch but could not get any PCI devices to
come up with the sifive_u machine. Depending on the kernel I tried, it
either failed to initialize a Xilinx PCIe (likely due to a mismatch with
the DT) or it appears to successfully initialize a Microsemi device but
did not enumerate any devices underneath.

In any case, it would be nice if the Microsemi/Xilinx confusion was at
least explained in the commit message.

Thanks,

Logan

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Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts, (continued)
- [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/11/21
  - Re: [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA, Logan Gunthorpe, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing, Alistair Francis, 2018/11/21
  - Re: [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing, Logan Gunthorpe, 2018/11/21
- [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
  - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe <=
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
    - Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21

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