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Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add dire
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions |
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Date: |
Mon, 19 Nov 2018 15:06:31 -0800 |
On Fri, Nov 16, 2018 at 9:10 AM Richard Henderson
<address@hidden> wrote:
>
> On 11/15/18 11:36 PM, Alistair Francis wrote:
> > + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
>
> Should avoid this when guest_base == 0, which happens fairly regularly for a
> 64-bit guest.
>
> > + /* Prefer to load from offset 0 first, but allow for overlap. */
> > + if (TCG_TARGET_REG_BITS == 64) {
> > + tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
> > + } else {
> > + tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
> > + tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
> > + }
>
> Comment sounds like two lines of code that's missing.
I can't figure out what this comment should be for. Why would we want
to prefer loading with an offset 0?
Alistair
>
> > + const TCGMemOp bswap = opc & MO_BSWAP;
> > +
> > + /* TODO: Handle byte swapping */
>
> Should assert rather than emit bad code.
>
> I do still plan to change tcg to allow backends to *not* handle byte swapping
> if they don't want. This will make the i386 and arm32 backends less icky.
>
>
> r~
- Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions, (continued)
[Qemu-riscv] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/11/15