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Re: [Qemu-ppc] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal.h to cpu.h |
Date: |
Fri, 8 Mar 2019 10:27:34 +1100 |
User-agent: |
Mutt/1.11.3 (2019-02-01) |
On Thu, Mar 07, 2019 at 06:05:16PM +0000, Mark Cave-Ayland wrote:
> It isn't possible to include internal.h from cpu.h so move the Vsr* macros
> into cpu.h alongside the other VMX/VSX register access functions.
>
> Signed-off-by: Mark Cave-Ayland <address@hidden>
Applied, thanks.
> ---
> target/ppc/cpu.h | 20 ++++++++++++++++++++
> target/ppc/internal.h | 19 -------------------
> 2 files changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 4a7df13c2d..d0580c6b6d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2563,6 +2563,26 @@ static inline bool lsw_reg_in_range(int start, int
> nregs, int rx)
> }
>
> /* Accessors for FP, VMX and VSX registers */
> +#if defined(HOST_WORDS_BIGENDIAN)
> +#define VsrB(i) u8[i]
> +#define VsrSB(i) s8[i]
> +#define VsrH(i) u16[i]
> +#define VsrSH(i) s16[i]
> +#define VsrW(i) u32[i]
> +#define VsrSW(i) s32[i]
> +#define VsrD(i) u64[i]
> +#define VsrSD(i) s64[i]
> +#else
> +#define VsrB(i) u8[15 - (i)]
> +#define VsrSB(i) s8[15 - (i)]
> +#define VsrH(i) u16[7 - (i)]
> +#define VsrSH(i) s16[7 - (i)]
> +#define VsrW(i) u32[3 - (i)]
> +#define VsrSW(i) s32[3 - (i)]
> +#define VsrD(i) u64[1 - (i)]
> +#define VsrSD(i) s64[1 - (i)]
> +#endif
> +
> static inline int fpr_offset(int i)
> {
> return offsetof(CPUPPCState, vsr[i].u64[0]);
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index f26a71ffcf..3ebbdf4da4 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -204,25 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8);
> EXTRACT_HELPER(DCMX, 16, 7);
> EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
>
> -#if defined(HOST_WORDS_BIGENDIAN)
> -#define VsrB(i) u8[i]
> -#define VsrSB(i) s8[i]
> -#define VsrH(i) u16[i]
> -#define VsrSH(i) s16[i]
> -#define VsrW(i) u32[i]
> -#define VsrSW(i) s32[i]
> -#define VsrD(i) u64[i]
> -#define VsrSD(i) s64[i]
> -#else
> -#define VsrB(i) u8[15 - (i)]
> -#define VsrSB(i) s8[15 - (i)]
> -#define VsrH(i) u16[7 - (i)]
> -#define VsrSH(i) s16[7 - (i)]
> -#define VsrW(i) u32[3 - (i)]
> -#define VsrSW(i) s32[3 - (i)]
> -#define VsrD(i) u64[1 - (i)]
> -#define VsrSD(i) s64[1 - (i)]
> -#endif
> static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
> {
> vsr->VsrD(0) = env->vsr[n].u64[0];
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v2 0/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal.h to cpu.h, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 6/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 1/7] target/ppc: introduce single fpr_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 4/7] target/ppc: introduce avr_full_offset() function, Mark Cave-Ayland, 2019/03/07