[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH v2 00/15] ppc: add POWER9 support to the PowerNV platf
Cédric Le Goater
[Qemu-ppc] [PATCH v2 00/15] ppc: add POWER9 support to the PowerNV platform
Thu, 7 Mar 2019 23:35:33 +0100
Here is the second round of the patchset adding support for the POWER9
processor to the PowerNV machine. It includes POWER9 models for the
PSI host bridge, the LPC controller, and a minimalist OCC, some
extensions of the CPU core model to support POWER9 XSCOM addresses and
a new PnvQuad model controlling the power management state of group of
four cores on a POWER9 processor.
It should bring the POWER9 PowerNV platform to the same level as
POWER8, that is without PHBs.
A new skiboot image is not provided yet because I would like first to
have a tagged version of skiboot including the recent changes removing
support for DD1. Will come later.
Hopefully, this is good enough for QEMU 4.0.
Changes in v2 :
- introduced Pnv8Psi (XICS) and Pnv9Psi (XIVE) models
- wrote a commit log for the changes in the LPC register ranges
- added a 'dt_isa_nodename' to the chip
- added new attributes to define XSCOM operations per CPU family and
a PSI IRQ number in the OCC class model
- added a new attribute to define XSCOM operations per CPU family
in the CPU core class model
Changes in v1 (since PnvXive was last sent) :
- fixed compilation on clang (forward declarations)
- simplified the hardwiring of the Physical CAM line. removed the
- removed 'hwaddr offset' from the get_tctx() XiveRouter handler. It
was a misunderstanding of the PC_THREAD_EN_REGx registers.
- changed the CPU machine_data presenter type to 'Object *' to accept
- introduced a new dt_populate() operation to the chip model
- introduced a new pic_print_info() operation to the chip model
- removed 'chip_id' from PnvXive.
- removed 'nr_irqs' and 'nr_ends' from PnvXive. Values are now
calculated from the VST settings done by FW.
- removed 'type' field from the XiveVstInfo struct describing the VSTs
- simplified pnv_xive_get_ic() grabbing a remote IC
- introduced a pnv_xive_vst_size() helper computing the size of a VST
table, direct or indirect. Used to computed the number of virtual
structures entries provisioned by FW.
- reworked pnv_xive_vst_addr_*() helpers. Fixed a bug when multiple
pages are in use.
- took into account the word_number when doing stores of the virtual
- the IPI and the END sub memory regions of the VC BAR are now
resized and mapped when the EDT is configured, depending on how the
VC region was segmented.
- the XiveSource and the XiveENDSource memory regions are now resized
and mapped when the VST are configured, depending on how much
virtual structures entries were provisioned by FW.
- removed PC_GCONF_CHIPID_OVR handling. Was for debug according to HW
designers. xive->chip->chip_id is now used as the block id when
- reworked pic_print_info() to use the number of virtual structures
entries provisioned by FW.
What has not changed (since PnvXive was sent) :
- GETFIELD/SETFIELD macros. It would break the compatibility with
skiboot in the register definitions. Still needs some thinking to
find a common ground. P10 material for QEMU and skiboot probably.
- The HW interface of XIVE is still bound to the register array. P10
support will determine which is the best approach.
Cédric Le Goater (15):
ppc/pnv: add a PSI bridge class model
ppc/pnv: add a PSI bridge model for POWER9
ppc/pnv: lpc: fix OPB address ranges
ppc/pnv: add a LPC Controller class model
ppc/pnv: add a 'dt_isa_nodename' to the chip
ppc/pnv: add a LPC Controller model for POWER9
ppc/pnv: add SerIRQ routing registers
ppc/pnv: add a OCC model class
ppc/pnv: add a OCC model for POWER9
ppc/pnv: extend XSCOM core support for POWER9
ppc/pnv: POWER9 XSCOM quad support
ppc/pnv: activate XSCOM tests for POWER9
ppc/pnv: add more dummy XSCOM addresses
ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9
target/ppc: add HV support for POWER9
include/hw/ppc/pnv.h | 19 +-
include/hw/ppc/pnv_core.h | 12 +
include/hw/ppc/pnv_lpc.h | 26 ++
include/hw/ppc/pnv_occ.h | 17 ++
include/hw/ppc/pnv_psi.h | 59 ++++-
include/hw/ppc/pnv_xscom.h | 18 +-
hw/ppc/pnv.c | 134 +++++++++--
hw/ppc/pnv_core.c | 187 ++++++++++++++-
hw/ppc/pnv_lpc.c | 306 +++++++++++++++++++++---
hw/ppc/pnv_occ.c | 127 ++++++++--
hw/ppc/pnv_psi.c | 404 ++++++++++++++++++++++++++++++--
hw/ppc/pnv_xscom.c | 33 ++-
target/ppc/translate_init.inc.c | 3 +-
tests/pnv-xscom-test.c | 2 -
14 files changed, 1231 insertions(+), 116 deletions(-)
- [Qemu-ppc] [PATCH v2 00/15] ppc: add POWER9 support to the PowerNV platform,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges, Cédric Le Goater, 2019/03/07
- [Qemu-ppc] [PATCH v2 09/15] ppc/pnv: add a OCC model for POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-ppc] [PATCH v2 13/15] ppc/pnv: add more dummy XSCOM addresses, Cédric Le Goater, 2019/03/07
- [Qemu-ppc] [PATCH v2 12/15] ppc/pnv: activate XSCOM tests for POWER9, Cédric Le Goater, 2019/03/07
- [Qemu-ppc] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9, Cédric Le Goater, 2019/03/07