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Re: [Qemu-ppc] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all

From: Richard Henderson
Subject: Re: [Qemu-ppc] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order
Date: Sun, 3 Mar 2019 15:32:35 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0

On 3/3/19 9:23 AM, Mark Cave-Ayland wrote:
> When VSX support was initially added, the fpr registers were added at
> offset 0 of the VSR register and the vsrl registers were added at offset
> 1. This is in contrast to the VMX registers (the last 32 VSX registers) which
> are stored in host-endian order.
> Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also
> stored in host endian order to match the VMX registers. This ensures that TCG
> vector operations involving mixed VMX and VSX registers will function
> correctly.
> Signed-off-by: Mark Cave-Ayland <address@hidden>
> ---
>  target/ppc/cpu.h      | 4 ++--
>  target/ppc/internal.h | 8 ++++----
>  target/ppc/machine.c  | 8 ++++----
>  3 files changed, 10 insertions(+), 10 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


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