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[Qemu-ppc] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPID
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPIDR is written |
Date: |
Fri, 15 Feb 2019 18:00:26 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
Our TCG TLB only tags whether it's a HV vs a guest access, so it must
be flushed when the LPIDR is changed.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 15 +++++++++++++++
target/ppc/translate_init.inc.c | 7 ++++++-
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c7de04e06896..fe293937c646 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -718,6 +718,7 @@ DEF_HELPER_2(store_ptcr, void, env, tl)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
DEF_HELPER_2(store_pidr, void, env, tl)
+DEF_HELPER_2(store_lpidr, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbl, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_atbl, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index b88493009609..c65d1ade15c2 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -117,6 +117,21 @@ void helper_store_pidr(CPUPPCState *env, target_ulong val)
tlb_flush(CPU(cpu));
}
+void helper_store_lpidr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ env->spr[SPR_LPIDR] = val;
+
+ /*
+ * We need to flush the TLB on LPID changes as we only tag HV vs
+ * guest in TCG TLB. Also the quadrants means the HV will
+ * potentially access and cache entries for the current LPID as
+ * well.
+ */
+ tlb_flush(CPU(cpu));
+}
+
void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
{
target_ulong hid0;
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 59e0b8676236..6f8b459e3b39 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -407,6 +407,11 @@ static void spr_write_pidr(DisasContext *ctx, int sprn,
int gprn)
gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
}
+static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
+}
+
static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
@@ -7876,7 +7881,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
spr_register_hv(env, SPR_LPIDR, "LPIDR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_lpidr,
0x00000000);
spr_register_hv(env, SPR_HFSCR, "HFSCR",
SPR_NOACCESS, SPR_NOACCESS,
--
2.20.1
- [Qemu-ppc] [PATCH 03/12] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, (continued)
- [Qemu-ppc] [PATCH 03/12] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 11/12] target/ppc: Support for POWER9 native hash, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 07/12] target/ppc: Add basic support for "new format" HPTE as found on POWER9, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 05/12] target/ppc: Cleanup 64-bit MMU includes, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 08/12] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 12/12] target/ppc: Basic POWER9 bare-metal radix MMU support, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPIDR is written,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH 01/12] target/ppc/spapr: Set LPCR:HR when using Radix mode, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 04/12] target/ppc: Fix #include guard in mmu-book3s-v3.h, Cédric Le Goater, 2019/02/15
- Re: [Qemu-ppc] [PATCH 00/12] ppc: add native hash and radix support for POWER9, David Gibson, 2019/02/19