[Qemu-ppc] [QEMU-PPC] [PATCH] ppc/tcg: Ignore bit 6 in the eieio instruction

[Suraj Jitindar Singh]

The kernel patch
"powerpc/64s: Add support for a store forwarding barrier at kernel entry/exit"
adds an eieio barrier instruction to kernel entry and exit points on
the POWER9 platform. The eieio instruction form used has bit 6 set.
This bit is ignored by hardware however under tcg it causes an illegal
instruction.

To allow these kernels to run under tcg, modify the eieio instruction
to ignore bit 6.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
---
 target/ppc/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3457d29f8e..b1ad1e2a22 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6496,7 +6496,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, 
PPC_STRING),
 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
-GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
+GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
-- 
2.13.6