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[Qemu-ppc] [PULL 01/15] target-ppc: optimize cmp translation
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 01/15] target-ppc: optimize cmp translation |
Date: |
Wed, 3 Jan 2018 15:24:05 +1100 |
From: "address@hidden" <address@hidden>
We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.
For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less than 10%. For softmmu, the
improvement is around 5%.
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4075fc8589..8a6bd329d0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -605,27 +605,22 @@ static opc_handler_t invalid_handler = {
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_temp_new_i32();
-
- tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
-
- tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ TCGv t1 = tcg_temp_new();
+ TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_movi_tl(t0, CRF_EQ);
+ tcg_gen_movi_tl(t1, CRF_LT);
+ tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1,
t0);
+ tcg_gen_movi_tl(t1, CRF_GT);
+ tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1,
t0);
- tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_trunc_tl_i32(t, t0);
+ tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
tcg_temp_free(t0);
- tcg_temp_free_i32(t1);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(t);
}
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
--
2.14.3
- [Qemu-ppc] [PULL 00/15] ppc-for-2.12 queue 20180103, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 01/15] target-ppc: optimize cmp translation,
David Gibson <=
- [Qemu-ppc] [PULL 03/15] sm501: Add panel hardware cursor registers also to read function, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 10/15] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 04/15] sm501: Add some more unimplemented registers, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 15/15] target/ppc: more use of the PPC_*() macros, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 12/15] spapr: Handle Decimal Floating Point (DFP) as an optional capability, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 05/15] ppc4xx_i2c: Implement basic I2C functions, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 06/15] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 14/15] hw/ide: Emulate SiI3112 SATA controller, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 07/15] spapr: Capabilities infrastructure, David Gibson, 2018/01/02
- [Qemu-ppc] [PULL 08/15] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability, David Gibson, 2018/01/02