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[Qemu-ppc] [PULL 07/34] target/ppc: Fix carry flag setting for shift alg
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 07/34] target/ppc: Fix carry flag setting for shift algebraic instructions |
Date: |
Tue, 17 Oct 2017 15:21:25 +1100 |
From: Sandipan Das <address@hidden>
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/int_helper.c | 16 ++++++++--------
target/ppc/translate.c | 12 ++++++++++++
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index da4e1a62c9..1c013a0ee3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -219,17 +219,17 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulong
value,
shift &= 0x1f;
ret = (int32_t)value >> shift;
if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
- env->ca = 0;
+ env->ca32 = env->ca = 0;
} else {
- env->ca = 1;
+ env->ca32 = env->ca = 1;
}
} else {
ret = (int32_t)value;
- env->ca = 0;
+ env->ca32 = env->ca = 0;
}
} else {
ret = (int32_t)value >> 31;
- env->ca = (ret != 0);
+ env->ca32 = env->ca = (ret != 0);
}
return (target_long)ret;
}
@@ -245,17 +245,17 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong
value,
shift &= 0x3f;
ret = (int64_t)value >> shift;
if (likely(ret >= 0 || (value & ((1ULL << shift) - 1)) == 0)) {
- env->ca = 0;
+ env->ca32 = env->ca = 0;
} else {
- env->ca = 1;
+ env->ca32 = env->ca = 1;
}
} else {
ret = (int64_t)value;
- env->ca = 0;
+ env->ca32 = env->ca = 0;
}
} else {
ret = (int64_t)value >> 63;
- env->ca = (ret != 0);
+ env->ca32 = env->ca = (ret != 0);
}
return ret;
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 606b605ba0..a81ff69d75 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2181,6 +2181,9 @@ static void gen_srawi(DisasContext *ctx)
if (sh == 0) {
tcg_gen_ext32s_tl(dst, src);
tcg_gen_movi_tl(cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_movi_tl(cpu_ca32, 0);
+ }
} else {
TCGv t0;
tcg_gen_ext32s_tl(dst, src);
@@ -2190,6 +2193,9 @@ static void gen_srawi(DisasContext *ctx)
tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
tcg_temp_free(t0);
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
tcg_gen_sari_tl(dst, dst, sh);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -2259,6 +2265,9 @@ static inline void gen_sradi(DisasContext *ctx, int n)
if (sh == 0) {
tcg_gen_mov_tl(dst, src);
tcg_gen_movi_tl(cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_movi_tl(cpu_ca32, 0);
+ }
} else {
TCGv t0;
tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
@@ -2267,6 +2276,9 @@ static inline void gen_sradi(DisasContext *ctx, int n)
tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
tcg_temp_free(t0);
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
tcg_gen_sari_tl(dst, src, sh);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
--
2.13.6
- [Qemu-ppc] [PULL 09/34] qom: introduce type_register_static_array(), (continued)
- [Qemu-ppc] [PULL 09/34] qom: introduce type_register_static_array(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 22/34] ppc: spapr: register 'host' core type along with the rest of core types, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 12/34] ppc: mac_newworld: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 16/34] ppc: virtex-ml507: replace cpu_model with cpu_type, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 18/34] ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 08/34] hw/ppc/spapr.c: abort unplug_request if previous unplug isn't done, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 19/34] ppc: move '-cpu foo, compat=xxx' parsing into ppc_cpu_parse_featurestr(), David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 33/34] spapr_pci: fail gracefully with non-pseries machine types, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 14/34] ppc: bamboo: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 31/34] ppc: pnv: consolidate type definitions and batch register them, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 07/34] target/ppc: Fix carry flag setting for shift algebraic instructions,
David Gibson <=
- [Qemu-ppc] [PULL 15/34] ppc: replace cpu_model with cpu_type on ref405ep, taihu boards, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 11/34] ppc: mpc8544ds/e500plat: use generic cpu_model parsing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 23/34] ppc: spapr: use cpu model names as tcg defaults instead of aliases, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 34/34] spapr_cpu_core: rewrite machine type sanity check, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 28/34] ppc: pnv: drop PnvCoreClass::cpu_oc field, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 29/34] ppc: pnv: define core types statically, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 21/34] ppc: spapr: use cpu type name directly, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 20/34] ppc: spapr: define core types statically, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 17/34] ppc: 40p/prep: replace cpu_model with cpu_type, David Gibson, 2017/10/17