Re: [Qemu-ppc] [RFC PATCH 00/26] guest exploitation of the XIVE interrupt controller (POWER9)

[Cédric Le Goater]

On 07/10/2017 12:24 PM, David Gibson wrote:
> On Wed, Jul 05, 2017 at 07:13:13PM +0200, Cédric Le Goater wrote:
>> On a POWER9 sPAPR machine, the Client Architecture Support (CAS)
>> negotiation process determines whether the guest operates with an
>> interrupt controller using the XICS legacy model, as found on POWER8,
>> or in XIVE exploitation mode, the newer POWER9 interrupt model. This
>> patchset is a first proposal to add XIVE support in the sPAPR machine.
>>
>> The first patches introduce the XIVE exploitation mode in CAS.
>>
>> Follow models for the XIVE interrupt controller, source and presenter.
>> We try to reuse the ICS and ICP models of XICS because the sPAPR
>> machine is tied to the XICSFabric interface and should be using a
>> common framework to be able to switch from one controller model to
>> another. To be discussed of course.
>>
>> Then comes support for the Hypervisor's call which are used to
>> configure the interrupt sources and the event/notification queues of
>> the guest.
>>
>> Finally, the last patches try to integrate the XIVE interrupt model in
>> the sPAPR machine and this not without a couple of serious hacks to
>> have something to test. See 'Caveats' below for more details.
>>
>> This is a first draft and I expect a lot of rewrite before it reaches
>> mainline QEMU. Nevertheless, it compiles, boots and can be used for
>> some testing.
> 
> 1 & 2 are straightforward enough that I've applied them already.  The
> rest will take longer to review, obviously.

For sure ... I don't expect anything soon. This is really a first 
draft to show the differences with XICS in the overall mechanics. 
The guest boots and perf are OK but the integration with the sPAPR 
machine is a mess. I also think the IRQ allocator is too complex 
for the sPAPR need and the Xive ICP object is useless. The changelogs 
are too short. 

I have continued working on CAS support and have found a solution
which allows a guest to switch interrupt controller: XICS <-> XIVE, 
under TCG and under KVM,kernel_irqchip=off. 

The XIVE ICP lives under ICPState for ease of use. As for the ICS, 
two different objects, XIVE and XICS, are maintained under the 
sPAPR machine in which the 'irqs' array needs to be synced when 
changing model. It's not too much of a hack I think and it is 
migration friendly. We will see when discussed.

I have pushed on github these changes and I am now exploring the 
abyssal zone of migration and cpu hot-plugging.

Cheers,

C.