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[Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 4/6] target/ppc: Change tlbie in
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 4/6] target/ppc: Change tlbie invalid fields for POWER9 support |
Date: |
Fri, 28 Apr 2017 16:58:24 +1000 |
The tlbie[l] instructions are used to invalidate TLB entries used to cache
address translations.
In ISAv3.00 (POWER9) more fields were added to the tblie[l] instructions
which were previously invalid. We don't care about any of these new fields
since we just invalidate the whole world anyway but we need to not
cause an illegal instruction exception when the instructions are called.
We also don't want to allow an older processor to have these fields set
since that would be invalid.
Add a new GEN_HANDLER for the ISAv3 instructions with the correct invalid
mask. These will only be generated to a POWER9 processor for now based on
the instruction flag. Also remove the PPC_MEM_TLBIE instruction flag from
the POWER9 processor definition to ensure the old tlbie isn't generated.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
V3 -> V4:
- Instead of changing the invalid mask for the existing tlbie[l] generator
create a new one for POWER9 with the correct invalid mask
---
target/ppc/translate.c | 2 ++
target/ppc/translate_init.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e8aa83d..9995bd6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6553,6 +6553,8 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
* different ISA versions */
GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
+GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 57dc098..e2fd6f6 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8950,7 +8950,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBSYNC |
PPC_64B | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
--
2.5.5
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 0/6] target/ppc: Implement POWER9 pseries TCG RADIX Support, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 2/6] target/ppc: Flush TLB on write to PIDR, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbie to check privilege level based on GTSE, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 1/6] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 4/6] target/ppc: Change tlbie invalid fields for POWER9 support,
Suraj Jitindar Singh <=
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 5/6] target/ppc: Implement ISA V3.00 radix page fault handler, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 6/6] target/ppc: Enable RADIX mmu mode for pseries TCG guest, Suraj Jitindar Singh, 2017/04/28