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[Qemu-ppc] [PATCH v3 6/6] target/ppc: do not reset reserve_addr in exec_
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v3 6/6] target/ppc: do not reset reserve_addr in exec_enter |
Date: |
Thu, 27 Apr 2017 10:48:24 +0530 |
In case when atomic operation is not supported, exit_atomic is called
and we stop the world and execute the atomic operation. This results
in a following call chain:
tcg_gen_atomic_cmpxchg_tl()
-> gen_helper_exit_atomic()
-> HELPER(exit_atomic)
-> cpu_loop_exit_atomic() -> EXCP_ATOMIC
-> qemu_tcg_cpu_thread_fn() => case EXCP_ATOMIC
-> cpu_exec_step_atomic()
-> cpu_step_atomic()
-> cc->cpu_exec_enter() = ppc_cpu_exec_enter()
Sets env->reserve_addr = -1;
But by the time it return back, the reservation is erased and the code
fails, this continues forever and the lock is never taken.
Instead set this in powerpc_excp()
Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do,
let us get rid of the function.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/excp_helper.c | 3 +++
target/ppc/translate_init.c | 9 ---------
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f4ee7aa..a6bcb47 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -728,6 +728,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
+ /* Reset the reservation */
+ env->reserve_addr = -1;
+
/* Any interrupt is context synchronizing, check if TCG TLB
* needs a delayed flush on ppc64
*/
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index e82e3e6..9b048cd 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10436,14 +10436,6 @@ static bool ppc_cpu_has_work(CPUState *cs)
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
-static void ppc_cpu_exec_enter(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- env->reserve_addr = -1;
-}
-
/* CPUClass::reset() */
static void ppc_cpu_reset(CPUState *s)
{
@@ -10660,7 +10652,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void
*data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
#endif
- cc->cpu_exec_enter = ppc_cpu_exec_enter;
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
cc->write_elf32_note = ppc32_cpu_write_elf32_note;
--
2.9.3
- [Qemu-ppc] [PATCH v3 0/6] The series enables Multi-Threaded TCG on PPC64, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 1/6] target/ppc: Emulate LL/SC using cmpxchg helpers, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 2/6] cputlb: handle first atomic write to the page, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 3/6] target/ppc: Generate fence operations, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 4/6] cpus: Fix CPU unplug for MTTCG, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 5/6] tcg: enable MTTCG by default for PPC64 on x86, Nikunj A Dadhania, 2017/04/27
- [Qemu-ppc] [PATCH v3 6/6] target/ppc: do not reset reserve_addr in exec_enter,
Nikunj A Dadhania <=